Patent application number | Description | Published |
20080197513 | BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS - A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress. | 08-21-2008 |
20080233366 | STRUCTURE AND METHOD FOR SiCOH INTERFACES WITH INCREASED MECHANICAL STRENGTH - Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration. | 09-25-2008 |
20080265381 | SiCOH DIELECTRIC - A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound. | 10-30-2008 |
20080265382 | Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same - A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method. | 10-30-2008 |
20080265415 | Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same - A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method. | 10-30-2008 |
20080277796 | ELECTRONIC STRUCTURES UTILIZING ETCH RESISTANT BORON AND PHOSPHORUS MATERIALS AND METHODS TO FORM SAME - A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention. | 11-13-2008 |
20090061237 | LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT - A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking —(CH | 03-05-2009 |
20090061649 | LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT - A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking —(CH | 03-05-2009 |
20090203225 | SiCOH FILM PREPARATION USING PRECURSORS WITH BUILT-IN POROGEN FUNCTIONALITY - A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving group. The use of an organosilicon precursor containing a molecular scale sacrificial leaving group enables control of the pore size at the nanometer scale, control of the compositional and structural uniformity and simplifies the manufacturing process. Moreover, fabrication of a dielectric film from a single precursor enables better control of the final porosity in the film and a narrower pore size distribution resulting in better mechanical properties at the same value of dielectric constant. | 08-13-2009 |
20090297729 | MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE - The present invention provides a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD. The inventive composite material is also characterized by the substantial absence of the broad distribution of larger sized pores which is prevalent in prior art porous composite materials. The porous composite material includes a first solid phase having a first characteristic dimension and a second solid phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less. | 12-03-2009 |
20090311859 | METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY - A method of fabricating an interconnect structure on a substrate includes steps of: providing a dielectric with at least one etched opening; filling the at least one etched opening with at least one conductive material; planarizing the conductive material to provide a planarized structure; subjecting the planarized structure to a plasma preclean process; and exposing the planarized structure to a silylating repair agent which is a silane derivative; and forming a dielectric cap layer on the planarized structure. | 12-17-2009 |
20110101489 | SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME - A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH | 05-05-2011 |
20110233513 | ENHANCED BONDING INTERFACES ON CARBON-BASED MATERIALS FOR NANOELECTRONIC DEVICES - Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material. | 09-29-2011 |
20110241200 | ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES - An ultra low dielectric constant material is disclosed. The ultra-low dielectric constant material comprises a three dimensional random network porous dielectric comprising atoms of Si, C, O, and H. The ultra-low dielectric constant material also comprises a dielectric constant of not more than 2.6. The ultra-low dielectric constant material further comprises a carbon concentration of at least 15% and a content of carbon that is bonded as —CH2-groups, wherein a concentration of carbon is greater than a concentration of carbon in an ultra low dielectric constant material formed by using a single step ultra-violet curing process. | 10-06-2011 |
20110271141 | Non-Volatile Memory Based Reliability and Availability Mechanisms for a Computing Device - Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip. | 11-03-2011 |
20110271161 | On-Chip Non-Volatile Storage of a Test-Time Profile for Efficiency and Performance Control - Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified. | 11-03-2011 |
20120032311 | MULTI COMPONENT DIELECTRIC LAYER - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. | 02-09-2012 |
20120205626 | SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP - A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device. | 08-16-2012 |
20120261793 | ELECTRICAL FUSE AND METHOD OF MAKING THE SAME - An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided. | 10-18-2012 |
20120306017 | WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS - An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET). | 12-06-2012 |
20120306018 | BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH - A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer. | 12-06-2012 |
20120308735 | ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES - A method for fabricating an ultra low dielectric constant material is disclosed. The method includes placing a substrate into a deposition reactor. A first precursor is flowed into the deposition reactor. The first precursor is a matrix precursor. A second precursor is flowed into the deposition reactor. The second precursor is a porogen precursor. A preliminary film is deposited onto the substrate based on the first and second precursors. The preliminary film includes Si, C, O, and H atoms. A first ultraviolet curing step is performed on the substrate including the preliminary film at a first temperature. At least a second ultraviolet curing step is performed on the substrate including the preliminary film at a second temperature. | 12-06-2012 |
20120328796 | MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE - A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less | 12-27-2012 |
20120329287 | LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT - A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CH | 12-27-2012 |
20130087923 | MULTI COMPONENT DIELECTRIC LAYER - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si═C, B, Si═B, Si═B═C, and B═C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto. | 04-11-2013 |
20130175680 | DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH - A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH | 07-11-2013 |
20130203246 | SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP - A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device. | 08-08-2013 |
20140021581 | LOW COST ANTI-FUSE STRUCTURE - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 01-23-2014 |
20140024210 | LOW COST ANTI-FUSE STRUCTURE AND METHOD TO MAKE SAME - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 01-23-2014 |
20140042627 | ELECTRONIC STRUCTURE CONTAINING A VIA ARRAY AS A PHYSICAL UNCLONABLE FUNCTION - A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure. | 02-13-2014 |
20140042628 | STRUCTURE WITH SUB-LITHOGRAPHIC RANDOM CONDUCTORS AS A PHYSICAL UNCLONABLE FUNCTION - A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit. | 02-13-2014 |
20140050860 | MATERIALS CONTAINING VOIDS WITH VOID SIZE CONTROLLED ON THE NANOMETER SCALE - A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less | 02-20-2014 |
20140117457 | BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH - An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. | 05-01-2014 |
20140120667 | BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH - A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer. | 05-01-2014 |
20140312986 | TUNABLE INTERCONNECT STRUCTURES, AND INTEGRATED CIRCUIT CONTAINING THE SAME - Tunable interconnect structures, integrated circuits containing the tunable interconnect structures and methods of manufacturing the same are disclosed. The interconnect transmission line structure includes a signal conductor and a plurality of conductors in proximity to the signal conductor. The structure further includes one or more switchable conductors in proximity to at least the signal conductor. The one or more switchable conductors has a programmable wiring switch with a terminal connected to the one or more switchable conductors and another terminal connected to ground. | 10-23-2014 |