| Patent application number | Description | Published |
|---|
| 20090278621 | Pulse Width Modulation Dead Time Compensation Method and Apparatus - Dead time compensated complementary pulse width modulation (PWM) signals are derived from a PWM generator by first applying time period compensation to the PWM generator signal based upon the direction of current flow in an inductive load being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal for producing complementary dead time compensated PWM signals for controlling power switching circuits driving the inductive load. | 11-12-2009 |
| 20100079078 | Using Pulse Density Modulation for Controlling Dimmable Electronic Lighting Ballasts - Pulse Density Modulation (PDM) controls light brightness from a fluorescent lamp by applying voltages to the lamp filaments at two or more sequential signal frequencies. A low frequency, an intermediate frequency and a high frequency may be used to control the brightness of the lamp. The lamp gas ionizes to produce light only when the low or intermediate frequency voltage is applied thereto. The lamp gas is not ionized at the high frequency voltage, but the high frequency voltage keeps the lamp filaments warm during low brightness conditions. The low frequency, intermediate frequency, no and/or high frequency voltages have time periods that occur within a modulation frame time period that repeats continuously. The ratio of the low frequency and intermediate frequency time periods, and the no and/or high frequency voltage time periods determine the light output of the fluorescent lamp, and also maintain a proper temperature of the filaments. | 04-01-2010 |
| 20100259179 | HIGH RESOLUTION PULSE WIDTH MODULATION (PWM) FREQUENCY CONTROL USING A TUNABLE OSCILLATOR - A fluorescent lamp light intensity dimming control generates a pulse width modulation (PWM) signal at about a fifty percent duty cycle and has very fine frequency change granularity to allow precise and smooth light dimming capabilities. Intermediate PWM signal frequencies between the frequencies that are normally generated from values in a period register of the PWM generator are provided with a variable frequency clock source to the PWM generator. Selection of each frequency from the plurality of frequencies available from the variable frequency clock source may be determined from a value stored in a variable frequency clock register. A microcontroller may be used to select appropriate frequencies for dimming control of the fluorescent lamp from the variable frequency clock source, and the period and duty cycle values used in generating the PWM signal at about a fifty percent duty cycle. | 10-14-2010 |
| 20130057330 | ENHANCED COMPLEMENTARY WAVEFORM GENERATOR - An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed. | 03-07-2013 |
| 20130080819 | MICROCONTROLLER WITH SCHEDULING UNIT - A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register. | 03-28-2013 |
| 20130195124 | TIMEBASE PERIPHERAL - A microcontroller has a timebase driven by a clock signal, wherein the timebase has a reset input and an output coupled with a comparator. The comparator is further coupled with a register and is operable to generate a synchronization output signal if the timebase matches the register value. The microcontroller further has a first multiplexer receiving the synchronization output signal from the comparator and further receiving at least one event signal generated by a unit other than the timebase, wherein the first multiplexer is operable to select either the synchronization output signal or the at least one event signal as a timebase synchronization output signal. | 08-01-2013 |
| 20130198500 | PERIPHERAL SPECIAL FUNCTION REGISTER WITH SOFT-RESET DISABLE - A microcontroller has a plurality of peripherals, and at least one control bit, wherein the control bit controls a reset of at least one peripheral such that in a first mode any type of reset resets the at least one peripheral of said plurality of peripherals and in a second mode only a power supply reset resets the at least one peripheral. | 08-01-2013 |
| 20130241626 | INPUT CAPTURE PERIPHERAL WITH GATING LOGIC - A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated. | 09-19-2013 |
| 20140040654 | TIMEBASE PERIPHERAL - A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register. | 02-06-2014 |
| 20140240020 | CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING - A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators. | 08-28-2014 |
| 20140254731 | Dithering Circuit for Serial Data Transmission - A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system clock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock. | 09-11-2014 |
| 20140258566 | Dynamic Pause Period Calculation for Serial Data Transmission - A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is operable to determine an actual transmission length and calculate a length of a pause pulse and to add the pause pulse at the end of a transmission to generate a transmission having a constant length. | 09-11-2014 |
