Patent application number | Description | Published |
20110267127 | Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC - An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA. | 11-03-2011 |
20120025918 | APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR - An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples. | 02-02-2012 |
20120027143 | CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF - One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock. | 02-02-2012 |
20130093469 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 04-18-2013 |
20130093470 | FREQUENCY SYNTHESIZER AND ASSOCIATED METHOD - A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided. | 04-18-2013 |
20130093471 | TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER - A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output. | 04-18-2013 |
20130094606 | MULTI-STAGE DIGITALLY-CONTROLLED POWER AMPLIFIER - A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal. | 04-18-2013 |
20130094607 | TRANSMITTER EMPLOYING PULLING MITIGATION MECHANISM AND RELATED METHOD THEREOF - A transmitter includes a power amplifier (PA) and a direct current (DC) voltage tuning circuit. The PA is arranged for receiving a radio-frequency (RF) clock derived from a clock source, and producing an output signal according to at least the RF clock. The DC voltage tuning circuit is arranged for tuning at least one DC voltage supplied to the PA for pulling mitigation of the clock source. A method of pulling mitigation of a source clock by a power amplifier (PA) includes adjusting a direct current (DC) voltage supplied to the PA. | 04-18-2013 |
20130094611 | DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL - A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal. | 04-18-2013 |
20130162361 | OSCILLATOR CIRCUIT AND METHOD FOR GENERATING AN OSCILLATION - The invention relates to an oscillator circuit, comprising a clipping element for generating a clipped signal, and a first amplification stage for amplifying and filtering the clipped signal to obtain a filtered signal, wherein the clipping element is configured to generate the clipped signal upon the basis of the filtered signal. | 06-27-2013 |
20130187688 | POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF - A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result. | 07-25-2013 |
20130187800 | METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC MISMATCH - A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step. | 07-25-2013 |
20130188749 | POLAR TRANSMITTER HAVING DIGITAL PROCESSING BLOCK USED FOR ADJUSTING FREQUENCY MODULATING SIGNAL FOR FREQUENCY DEVIATION OF FREQUENCY MODULATED CLOCK AND RELATED METHOD THEREOF - A polar transmitter includes a frequency modulating path, a clock divider and a digital processing block. The frequency modulating path is arranged for generating a frequency modulated clock in response to a frequency modulating signal. The clock divider is coupled to the frequency modulated clock, and arranged for generating a down-divided clock. The digital processing block is coupled to the down-divided clock, and arranged for generating the frequency modulating signal, wherein the frequency modulating signal is adjusted for frequency deviation of the frequency modulated clock. A method for polar transmission includes: generating a frequency modulated clock in response to a frequency modulating signal; dividing a frequency of said frequency modulated clock to generate a down-divided clock; and generating said frequency modulating signal according to said down-divided clock, wherein said frequency modulating signal is adjusted for frequency deviation of said frequency modulated clock. | 07-25-2013 |
20130188754 | TRANSMITTER AND FREQUENCY DEVIATION REDUCTION METHOD THEREOF - A transmitter is provided. The transmitter includes a phase/frequency deviation input, a controller and a frequency modulating path. The phase/frequency deviation input receives multiple phase/frequency deviation samples. The controller outputs a modified phase/frequency deviation signal and generates a phase/frequency deviation carry-out signal in response to the phase/frequency deviation samples and a previous time sample of the phase/frequency deviation carry-out signal. The frequency modulating path performs frequency modulation in response to the modified phase/frequency deviation signal and outputs a frequency modulated carrier signal. | 07-25-2013 |
20130191061 | METHOD AND APPARATUS OF ESTIMATING/CALIBRATING TDC GAIN - A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step. | 07-25-2013 |
20130285724 | CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF - A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock. | 10-31-2013 |
20130301754 | FREQUENCY MODULATOR HAVING DIGITALLY-CONTROLLED OSCILLATOR ARRANGED FOR RECEIVING MODULATION TUNING WORD AND PHASE-LOCKED LOOP TUNING WORD AND/OR RECEIVING FRACTIONAL TUNING WORD OBTAINED THROUGH ASYNCHRONOUS SAMPLING AND INTEGER TUNING WORD - A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word. | 11-14-2013 |
20130343173 | TRANSMITTER - The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive. | 12-26-2013 |
20140077890 | CLASS-F CMOS OSCILLATOR - A novel and useful oscillator topology demonstrating an improved phase noise performance that exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The oscillator is based on enforcing a pseudo-square voltage waveform around an LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. Alternatively, the oscillator is based on enforcing clipped oscillation waveform by increasing the second harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. | 03-20-2014 |
20140080436 | HIGH-IF SUPERHETERODYNE RECEIVER INCORPORATING HIGH-Q COMPLEX BAND PASS FILTER - A novel and useful reconfigurable superheterodyne receiver that employs a 3 | 03-20-2014 |
20140085012 | HIGH RESOLUTION MILLIMETER WAVE DIGITALLY CONTROLLED OSCILLATOR WITH RECONFIGURABLE DISTRIBUTED METAL CAPACITOR PASSIVE RESONATORS - A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than −90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz. | 03-27-2014 |
20140171009 | Radio Frequency Receiver - A radio frequency receiver for receiving an analog radio frequency signal, the radio frequency receiver comprising a sampling mixer being configured to sample the analog radio frequency signal using a predetermined sampling rate (f | 06-19-2014 |
20140185663 | INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD FOR IMPROVED AMPLITUDE RESOLUTION OF AN RF-DAC - An integrated circuit includes: a digitally-controlled power generation stage for converting an input signal to a radio frequency (RF) carrier, the digitally-controlled power generation stage including a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal according to a fractional word and operably coupleable to the plurality of selectable switching devices of the digitally-controlled power generation stage; wherein the PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope of the RF carrier output from the digitally-controlled power generation stage. | 07-03-2014 |
20140194081 | Superheterodyne Receiver - The invention relates to a superheterodyne receiver, comprising: a sampling mixer being configured to sample an analog radio frequency signal using a certain sampling rate (f | 07-10-2014 |
20140210528 | PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC) - One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal. | 07-31-2014 |
20140240047 | DIGITALLY-CONTROLLED POWER AMPLIFIER WITH BANDPASS FILTERING/TRANSIENT WAVEFORM CONTROL AND RELATED DIGITALLY-CONTROLLED POWER AMPLIFIER CELL - A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal. | 08-28-2014 |
20140320215 | Oscillator - An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator. | 10-30-2014 |
20140354376 | HIGH ORDER DISCRETE TIME CHARGE ROTATING PASSIVE INFINITE IMPULSE RESPONSE FILTER - A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low-pass filter is presented. The filter utilizes capacitors and a g | 12-04-2014 |
20140355720 | WIDEBAND FM DEMODULATION BY INJECTION-LOCKED DIVISION OF FREQUENCY DEVIATION - A novel and useful wideband FM demodulator operating across an 8 GHz IF bandwidth for application in low-power, wideband heterodyne receivers. The demodulator includes an n-stage ring oscillator that is injection locked to a wideband input signal. Locking to the input frequency, it divides the FM deviation by n, thereby facilitating as well as reducing the energy required for wideband demodulation. The quadrature-phased output of the ring oscillator is auto correlated using a low-power folded CMOS mixer capable of detecting FM up to 400 Mb/s over a 2-10 GHz IF frequency range. | 12-04-2014 |
20150043699 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 02-12-2015 |
20150102868 | FREQUENCY MODULATOR HAVING DIGITALLY-CONTROLLED OSCILLATOR WITH MODULATION TUNING AND PHASE-LOCKED LOOP TUNING - A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word. | 04-16-2015 |
20150116018 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period. | 04-30-2015 |
20150137898 | Oscillator Buffer and Method for Calibrating the Same - A buffering circuit for buffering an oscillator signal. The buffering circuit includes a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an oscillator signal at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor. The buffering circuit also includes a control circuit arranged for receiving an output signal provided by the inverter circuits, for deriving information on the DC level of the output signal, and for adjusting a voltage transfer curve expressing a relationship between a voltage at the input and output of the buffering circuit, by switching on or off the additional PMOS and NMOS transistors based on the derived information | 05-21-2015 |
20150214926 | DISCRETE-TIME FILTER - A discrete-time filter for filtering an input signal comprises a switched capacitor network, the switched capacitor network comprising an input and an output, a number of switched capacitor paths arranged in parallel between the input and the output, each switched capacitor path comprising a capacitor, and a switch circuitry for switching each capacitor at a different time instant for outputting a filtered input signal. | 07-30-2015 |
20150288369 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 10-08-2015 |
20150372665 | QUADRATURE LC TANK DIGITALLY CONTROLLED RING OSCILLATOR - A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on. | 12-24-2015 |