Patent application number | Description | Published |
20090095218 | Temperature controlled showerhead - A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger. | 04-16-2009 |
20090095219 | Temperature controlled showerhead - A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger. | 04-16-2009 |
20090095220 | TEMPERATURE CONTROLLED SHOWERHEAD - A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger. | 04-16-2009 |
20110256726 | PLASMA ACTIVATED CONFORMAL FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film. | 10-20-2011 |
20130189854 | METHOD FOR DEPOSITING A CHLORINE-FREE CONFORMAL SIN FILM - Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor. | 07-25-2013 |
20140141626 | METHOD FOR DEPOSITING A CHLORINE-FREE CONFORMAL SIN FILM - Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor. | 05-22-2014 |
20140158792 | TEMPERATURE CONTROLLED SHOWERHEAD - A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger. | 06-12-2014 |
20140209562 | PLASMA ACTIVATED CONFORMAL FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film. | 07-31-2014 |
Patent application number | Description | Published |
20110113198 | Selective searching in shared cache - The present invention discloses a method comprising: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. The method further includes extending cache allocation logic to control a tag comparison operation by using a bit to provide a hint from IO devices that certain ways will not have requested data. | 05-12-2011 |
20120079235 | APPLICATION SCHEDULING IN HETEROGENEOUS MULTIPROCESSOR COMPUTING PLATFORMS - Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed. | 03-29-2012 |
20120173907 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING - Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption. | 07-05-2012 |
20140092014 | MULTI-MODAL TOUCH SCREEN EMULATOR - Systems and methods may provide for capturing a user input by emulating a touch screen mechanism. In one example, the method may include identifying a point of interest on a front facing display of the device based on gaze information associated with a user of the device, identifying a hand action based on gesture information associated with the user of the device, and initiating a device action with respect to the front facing display based on the point of interest and the hand action. | 04-03-2014 |
20140095794 | Apparatus and Method For Reducing The Flushing Time Of A Cache - A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state. | 04-03-2014 |
20140177955 | SYSTEM AND METHOD FOR ADAPTIVE SKIN TONE DETECTION - A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects. | 06-26-2014 |
Patent application number | Description | Published |
20120011480 | Logic-Driven Layout Verification - A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data. | 01-12-2012 |
20150058818 | PROGRAMMABLE PATTERN AWARE VOLTAGE ANALYSIS - This application discloses a voltage analysis tool to perform a static power aware analysis on a circuit design without having to simulate the circuit design. The voltage analysis tool can determine a set of components in the circuit design corresponds to a design pattern representing a voltage-transition device, and set an output voltage for the set of components based, at least in part, on characteristics of the voltage-transition device. The voltage analysis tool can propagate the output voltage to other portions of the circuit design, and determine whether the portions of the circuit design receiving the output voltage have a rule violation. | 02-26-2015 |
20150067621 | Logic-Driven Layout Pattern Analysis - A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. The selected physical design data corresponding to the specified logical component is then compared with a defined geometric element pattern, to determine if the corresponding physical design data matches the defined pattern. The results of the match analysis can be reported to a user as visual images, new design data, or both. Alternately or additionally, the selected physical design data may be modified based upon the results of the match analysis. | 03-05-2015 |
20150143318 | DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS - Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values. | 05-21-2015 |
Patent application number | Description | Published |
20090063773 | Technique to enable store forwarding during long latency instruction execution - A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold store operations in program order while independent load instructions are satisfied during a time in which a high-latency instruction is being processed. After the high-latency instruction is processed, the store operations can be restored in program order without searching the storage structure. | 03-05-2009 |
20090119459 | LATE LOCK ACQUIRE MECHANISM FOR HARDWARE LOCK ELISION (HLE) - A method and apparatus for a late lock acquire mechanism is herein described. In response to detecting a late-lock acquire event, such as expiration of a timer, a full cachet set, and an irrevocable event, a late-lock acquire may be initiated. Consecutive critical sections are stalled until a late-lock acquire is completed utilizing fields of access buffer entries associated with consecutive critical section operations. | 05-07-2009 |
20090328057 | SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX - A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied. | 12-31-2009 |
20100332868 | SQUELCH FILTRATION TO LIMIT FALSE WAKEUPS - Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed. | 12-30-2010 |
20110296216 | INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB - Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed. | 12-01-2011 |
20110296222 | DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING - Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. | 12-01-2011 |
20120117333 | CRITICAL SECTION DETECTION AND PREDICTION MECHANISM FOR HARDWARE LOCK ELISION - A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction. | 05-10-2012 |
20130339689 | LATER STAGE READ PORT REDUCTION - In some implementations, a register file has a plurality of read ports for providing data to a micro-operation during execution of the micro-operation. For example, the micro-operation may utilize at least two data sources, with at least one first data source being utilized at least one pipeline stage earlier than at least one second data source. A number of register file read ports may be allocated for executing the micro-operation. A bypass calculation is performed during a first pipeline stage to detect whether the at least one second data source is available from a bypass network. During a subsequent second pipeline stage, when the at least one second data source is detected to be available from the bypass network, the number of the read ports allocated to the micro-operation may be reduced. | 12-19-2013 |
20140181476 | Scheduler Implementing Dependency Matrix Having Restricted Entries - A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction. | 06-26-2014 |
20140189306 | ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION - An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled. | 07-03-2014 |
20140201505 | PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR - A processor includes one or more execution units to execute instructions of a plurality of threads and thread control logic coupled to the execution units to predict whether a first of the plurality of threads is ready for selection in a current cycle based on readiness of instructions of the first thread in one or more previous cycles, to predict whether a second of the plurality of threads is ready for selection in the current cycle based on readiness of instructions of the second thread in the one or more previous cycles, and to select one of the first and second threads in the current cycle based on the predictions. | 07-17-2014 |
20150089186 | STORE ADDRESS PREDICTION FOR MEMORY DISAMBIGUATION IN A PROCESSING DEVICE - A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations. | 03-26-2015 |
20150095627 | TWO LEVEL RE-ORDER BUFFER - In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution. | 04-02-2015 |
Patent application number | Description | Published |
20090077313 | METHOD AND APPARATUS TO MAINTAIN DATA INTEGRITY IN DISK CACHE MEMORY DURING AND AFTER PERIODS OF CACHE INACCESSIBILITY - A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available. | 03-19-2009 |
20110283139 | METHOD AND APPARATUS TO MAINTAIN DATA INTEGRITY IN DISK CACHE MEMORY DURING AND AFTER PERIODS OF CACHE INACCESSIBILITY - A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available. | 11-17-2011 |
20120001489 | AC ADAPTOR MINIMIZATION THROUGH ACTIVE PLATFORM POWER CONSUMPTION MANAGEMENT - Systems and methods of managing platform power consumption may involve determining a power consumption level of a platform based on at least in part a current supplied by an AC adaptor. A power limit of an integrated circuit in the platform can be determined based on at least in part the power consumption level of the platform, wherein the power level may be applied to the integrated circuit. | 01-05-2012 |
20120159201 | METHOD AND APPARATUS TO CONFIGURE THERMAL DESIGN POWER IN A MICROPROCESSOR - A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency. | 06-21-2012 |
20120241140 | APPARATUS, SYSTEM AND METHOD FOR AIRFLOW MONITORING AND THERMAL MANAGEMENT IN A COMPUTING DEVICE - Embodiments of an apparatus, system and method are described for monitoring an airflow and performing thermal management operations for a mobile computing device. An apparatus may comprise, for example, a heat generating component, an air mover, and a thermal management module to monitor one or more parameters of the air mover and to perform one or more thermal management operations based on one or more changes in the one or more parameters indicating one or more changes in an airflow for the apparatus. Other embodiments are described and claimed. | 09-27-2012 |
20140095897 | ELECTRONIC DEVICE AND METHOD TO EXTEND BATTERY LIFE - An electronic apparatus is provided that includes a processor, a voltage regulator, a battery controller and an embedded controller. The voltage regulator to receive an input voltage and to provide an output voltage to the processor. The battery controller to store electronic device information and to receive battery information related to a current battery power. The embedded controller to receive the electronic device information and the battery information from the battery controller, and the embedded controller to provide power information to the processor based on the received information. | 04-03-2014 |
20140173305 | METHOD AND APPARATUS FOR MANAGING COMPUTING SYSTEM POWER - An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level. | 06-19-2014 |
20140188302 | PRIORITY BASED INTELLIGENT PLATFORM PASSIVE THERMAL MANAGEMENT - Methods and apparatus relating to priority based intelligent platform passive thermal management are described. In one embodiment, the power consumption limit of one or more components of a platform is modified based on one or more thermal relationships between one or more power consuming components of the platform and one or more heat generating components of the platform. Furthermore, a first relationship of the one or more thermal relationships indicates an influence priority of a source component of the platform on a target component of the platform. Other embodiments are also claimed and disclosed. | 07-03-2014 |
20140189378 | TABLE DRIVEN MULTIPLE PASSIVE TRIP PLATFORM PASSIVE THERMAL MANAGEMENT - Methods and apparatus relating to table driven multiple passive trip, platform passive thermal management are described. In one embodiment, the power consumption limit of one or more components of a platform is modified based on one or more thermal relationships between one or more power consuming components of the platform and one or more heat generating components of the platform. Furthermore, a first relationship of the one or more thermal relationships indicates a mapping between a plurality of temperature thresholds and a corresponding plurality of performance limits. Other embodiments are also claimed and disclosed. | 07-03-2014 |