Patent application number | Description | Published |
20140203344 | 3D MEMORY - Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension. | 07-24-2014 |
20140264542 | MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER - Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier. | 09-18-2014 |
20150041879 | SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION OF SAME - Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures. | 02-12-2015 |
20150140797 | 3D MEMORY - Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension. | 05-21-2015 |
20150270280 | STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT - A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same. | 09-24-2015 |
20150287734 | MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER - Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier. | 10-08-2015 |
Patent application number | Description | Published |
20140162504 | HELICOIL SPRING BACKING SOCKET - Methods of forming a socket assembly and associated structures formed thereby are described. Those methods and structures may include forming a socket assembly comprising a socket body having a plurality of vertical openings, wherein contact assemblies are disposed within individual vertical openings. The contact assemblies comprise a compression spring surrounding an insulated conductive wire. | 06-12-2014 |
20150214665 | TWO PIECE SHIELDED SOCKET - A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via. | 07-30-2015 |
20150318630 | DOUBLE-MATED EDGE FINGER CONNECTOR - A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board. | 11-05-2015 |
Patent application number | Description | Published |
20150026676 | SYSTEMS AND METHODS FOR INSTANTLY RESTORING VIRTUAL MACHINES IN HIGH INPUT/OUTPUT LOAD ENVIRONMENTS - A computer-implemented method for instantly restoring virtual machines in high input/output load environments may include (1) identifying a hypervisor that is configurable to maintain simultaneous connections to multiple datastores of a network-attached-storage system, (2) receiving a request to activate a new virtual machine on the hypervisor, (3) determining a usage of at least one connection from the hypervisor to at least one datastore of the network-attached-storage system, and (4) selecting, based on the usage of the connection, a designated connection from the hypervisor to a designated datastore of the network-attached storage system for use by the new virtual machine to store data on the network-attached-storage system. Various other methods, systems, and computer-readable media are also disclosed. | 01-22-2015 |
20150186044 | SYSTEMS AND METHODS FOR IMPROVING SNAPSHOT PERFORMANCE - Techniques for improving snapshot performance are disclosed. In one embodiment, the techniques may be realized as a method for improving snapshot performance comprising initiating change block tracking for each unit of storage associated with each of a plurality of virtual machines, creating backup images of each unit of storage associated with each of the plurality of virtual machines, quiescing each of the plurality of virtual machines, and creating snapshots of each unit of storage associated with each of the plurality of virtual machines. The techniques may include identifying one or more changed blocks in at least one of the backup images using the change block tracking, editing the at least one of the backup images by replacing the identified one or more changed blocks using corresponding blocks from at least one snapshot of the snapshots, and releasing the at least one snapshot based upon a determination that editing has completed. | 07-02-2015 |
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20110296516 | INTEGRATED FIREWALL, IPS, AND VIRUS SCANNER SYSTEM AND METHOD - A system, method and computer program product are provided including a router and a security sub-system coupled to the router. Such security sub-system includes a plurality of virtual firewalls, a plurality of virtual intrusion prevention systems (IPSs), and a plurality of virtual virus scanners. Further, each of the virtual firewalls, IPSs, and virus scanners is assigned to at least one of a plurality of user and is configured in a user-specific. | 12-01-2011 |
20110296527 | INTEGRATED FIREWALL, IPS, AND VIRUS SCANNER SYSTEM AND METHOD - A system, method and computer program product are provided including a router and a security sub-system coupled to the router. Such security sub-system includes a plurality of virtual firewalls, a plurality of virtual intrusion prevention systems (IPSs), and a plurality of virtual virus scanners. Further, each of the virtual firewalls, IPSs, and virus scanners is assigned to at least one of a plurality of user and is configured in a user-specific. | 12-01-2011 |