Patent application number | Description | Published |
20140110047 | BONDING APPARATUS AND METHOD OF BONDING COMPONENT ON SUBSTRATE USING THE SAME - A bonding apparatus configured to bond a component on a substrate is presented. The apparatus includes a stage, a push member, a support member and a compression member. The stage fixes the substrate in place and by using at least one first suction part formed in the stage. The push member is disposed above the stage and pushes the substrate fixed to the stage to support the substrate on the stage. At least one second suction part is formed in the support member to attach to a pad part of the substrate. The compression member compresses the component into the pad part fixed to the support member. | 04-24-2014 |
20140261183 | COATING APPARATUS - A coating apparatus including an evaporation part, a thermal decomposition part, a deposition chamber, a vacuum pump, and a discharge pipe. The deposition chamber includes an upper portion, a lower portion facing the upper portion, and a sidewall portion connecting the upper portion and the lower portion to each other and including an inlet, first outlet, a second outlet, a third outlet and a fourth outlet. The discharge pipe includes a first auxiliary pipe connected to the first outlet and the second outlet, a second auxiliary pipe connected to the third outlet and the fourth outlet, an intermediate pipe connected to the first auxiliary pipe and the second auxiliary pipe, and a main pipe connected to the intermediate pipe. The vacuum pump is configured to discharge a portion of the monomer of the deposition material, which is not deposited, from the deposition chamber through the discharge pipe. | 09-18-2014 |
Patent application number | Description | Published |
20100146333 | Auxiliary power supply and user device including the same - A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO). | 06-10-2010 |
20100217927 | STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity. The logging process includes logging a location of the invalid data, and the invalidation process includes invalidating the invalid data. | 08-26-2010 |
20120144090 | STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity. | 06-07-2012 |
20130080689 | DATA STORAGE DEVICE AND RELATED DATA MANAGEMENT METHOD - A storage device performs data management for a nonvolatile memory device by detecting an allocation order of a first memory block, assigning page data of the first memory block to a second memory block or a third memory block having different erase counts based on the allocation order. | 03-28-2013 |
20150026516 | AUXILIARY POWER SUPPLY AND USER DEVICE INCLUDING THE SAME - A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO). | 01-22-2015 |
Patent application number | Description | Published |
20100287333 | DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A data storage device comprises a plurality of memory devices, a buffer memory, and a controller. The plurality of memory devices are connected to a plurality of channels and a plurality of ways. The buffer memory temporarily stores data to be written in the memory devices. The controller stores the data in the buffer memory based on channel and way information of the memory devices. | 11-11-2010 |
20120008394 | NONVOLATILE MEMORY SYSTEM AND REFRESH METHOD - A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence. | 01-12-2012 |
20130173954 | METHOD OF MANAGING BAD STORAGE REGION OF MEMORY DEVICE AND STORAGE DEVICE USING THE METHOD - A method of managing a bad storage region of a memory device may include detecting a bad page of a selected data block that has failed in one of a program operation, a read operation, and an erase operation on the memory device; and performing a mapping process so that the detected bad page is excluded from a storage region to which data is to be programmed, wherein remaining pages of the selected data block excluding the bad page are allowed to be used as a storage region in a garbage collection operation. | 07-04-2013 |
20130205073 | MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD THEREOF - A memory device, a memory system, and a programming method thereof. The memory system includes a memory controller configured to set first type offset information corresponding to a first type of data and set second type offset information corresponding to a second type of data; and a memory device configured to receive the first type offset information to program the first type of data in a first type of page that is read at a first speed and receive the second type offset information to program the second type of data in a second type of page that is read at a second speed, the first speed being different from the second speed. | 08-08-2013 |
20140160858 | NONVOLATILE MEMORY SYSTEM AND REFRESH METHOD - A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence. | 06-12-2014 |
Patent application number | Description | Published |
20090290320 | Structure for blocking an electromagnetic interference, wafer level package and printed circuit board having the same - A structure for blocking electromagnetic interference (EMI) may include at least one electromagnetic wave inducing member and an electromagnetic wave filtering member. The at least one electromagnetic wave inducing member may be provided to an electronic device to induce an electromagnetic wave applied to the electronic device. The electromagnetic wave filtering member may be provided to the electronic device to filter the electromagnetic wave induced by the at least one electromagnetic wave inducing member. Thus, the electromagnetic wave filtering member may remove the electromagnetic wave concentrated on the at least one electromagnetic wave inducing member, so that the electromagnetic wave applied to the electronic device may be effectively removed. As a result, circuits in the electronic device may be protected from the EMI. | 11-26-2009 |
20100258905 | SEMICONDUCTOR PACKAGE TO REMOVE POWER NOISE USING GROUND IMPEDANCE - A semiconductor package removes power noise by using a ground impedance. The semiconductor package includes an analog circuit block, a digital circuit block, an analog ground impedance structure, a digital ground impedance structure, and an integrated ground. The integrated ground and the analog circuit block are electrically connected via the analog ground impedance structure, and the integrated ground and the digital circuit block are electrically connected via the digital ground impedance structure, and an inductance of the analog ground impedance structure is greater than an inductance of the digital ground impedance structure. | 10-14-2010 |
20100276189 | SEMICONDUCTOR PACKAGE INCLUDING POWER BALL MATRIX AND POWER RING HAVING IMPROVED POWER INTEGRITY - In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states. | 11-04-2010 |
Patent application number | Description | Published |
20130048948 | INVERTER LOGIC DEVICES INCLUDING GRAPHENE FIELD EFFECT TRANSISTOR HAVING TUNABLE BARRIER - Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer. | 02-28-2013 |
20130048951 | GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER - According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer. | 02-28-2013 |
20130065022 | METHOD OF TRANSFERRING GRAPHENE USING TRENCH AND SUBSTRATE FOR RECEIVING GRAPHENE - A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate. | 03-14-2013 |
20130098540 | GRAPHENE-TRANSFERRING MEMBER, GRAPHENE TRANSFERRER, METHOD OF TRANSFERRING GRAPHENE, AND METHODS OF FABRICATING GRAPHENE DEVICE BY USING THE SAME - Graphene transferring members, graphene transferrer, methods of transferring graphene, and methods of fabricating a graphene device, may include a metal thin-film layer pattern and a graphene layer sequentially stacked on an adhesive member. The metal thin-film layer and the graphene layer may have the same shape. After transferring the graphene layer onto a transfer-target substrate during the fabrication of a graphene device, the metal thin-film layer is patterned to form electrodes on respective ends of the graphene layer by removing a portion of the metal thin-film layer. | 04-25-2013 |
20130175506 | THREE-DIMENSIONAL GRAPHENE SWITCHING DEVICE - A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate. | 07-11-2013 |
20140014905 | FIELD EFFECT TRANSISTOR USING GRAPHENE - According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode. | 01-16-2014 |
20140097403 | TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING GRAPHENE CHANNEL - According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate. | 04-10-2014 |
20140097404 | MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES - A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element. | 04-10-2014 |
20140117313 | GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER - According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode. | 05-01-2014 |
20140141600 | METHODS OF PREPARING GRAPHENE AND DEVICE INCLUDING GRAPHENE - A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film. | 05-22-2014 |
20140158989 | ELECTRONIC DEVICE INCLUDING GRAPHENE - According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10 | 06-12-2014 |
20140231752 | GRAPHENE DEVICE AND ELECTRONIC APPARATUS - A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor. | 08-21-2014 |
20140231820 | MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME - A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges. | 08-21-2014 |
20140299944 | GRAPHENE DEVICES AND METHODS OF FABRICATING THE SAME - A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate. | 10-09-2014 |
Patent application number | Description | Published |
20130082399 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes. | 04-04-2013 |
20130193588 | SEMICONDUCTOR PACKAGE - A semiconductor package includes first and second semiconductor elements electrically interconnected by a connection structure. The first and second semiconductor elements are joined by a protection structure that includes an adhesive layer surrounded by a retention layer. | 08-01-2013 |
20130299969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening. | 11-14-2013 |
20140134798 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes. | 05-15-2014 |
Patent application number | Description | Published |
20130062602 | Oxide Semiconductor Transistors And Methods Of Manufacturing The Same - Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions. | 03-14-2013 |
20130063400 | LIGHT-SENSING APPARATUS, METHOD OF DRIVING THE LIGHT-SENSING APPARATUS, AND OPTICAL TOUCH SCREEN APPARATUS INCLUDING THE LIGHT-SENSING APPARATUS - In one embodiment, a light-sensing apparatus includes a light-sensing pixel array that has a plurality of light-sensing pixels arranged in rows and columns; and a gate driver configured to provide the light-sensing pixels with a gate voltage and a reset signal that have inverted phases. Each of the light-sensing pixels includes a light sensor transistor configured to sense light and a switch transistor configured to output a light-sensing signal from the light-sensor transistor. The gate driver includes a plurality of gate lines connected to gates of the switch transistors, a plurality of reset lines connected to gates of the light sensor transistors, and a plurality of phase inverters each connected between a corresponding reset line and a gate line. Thus, when a gate voltage is applied to one of the plurality of gate lines, a reset signal with an inversed phase to the gate voltage may be applied to a corresponding reset line. | 03-14-2013 |
20130088460 | OPTICAL TOUCH SCREEN APPARATUS AND METHOD OF MANUFACTURING THE OPTICAL TOUCH SCREEN APPARATUS - An optical touch screen apparatus that includes a display pixel including a display cell and a driving transistor, the display cell configured to display an image and the driving transistor configured to turn on or off the display cell, the driving transistor having a double gate structure; and a light-sensing pixel including a light-sensing transistor and a switch transistor, the light-sensing transistor configured to sense incident light and the switch transistor configured to output data from the light-sensing transistor, the switch transistor having the double gate structure, wherein the double gate structure is a structure in which a bottom gate and a top gate are arranged such that a channel layer is disposed therebetween. The top gate may be formed together when forming a transparent electrode in the pixel, and thus even when the top gate is further included, the number of manufacturing processes is not increased. | 04-11-2013 |
20130168770 | HIGH-VOLTAGE OXIDE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer. | 07-04-2013 |
20130208204 | THIN FILM TRANSISTOR AND DISPLAY PANEL EMPLOYING THE SAME - A thin film transistor is provided. The transistor includes a gate; a first passivation layer covering the gate; a channel layer disposed on the first passivation layer; a source and a drain that are disposed on the first passivation layer and contact two sides of the channel layer; a second passivation layer covering the channel layer, the source, and the drain; first and second transparent electrode layers that are disposed on the second passivation layer and spaced apart from each other; a first transparent conductive via that penetrates the second passivation layer and connects the source and the first transparent electrode layer; and a second transparent conductive via that penetrates the second passivation layer and connects the drain and the second transparent electrode layer. A cross-sectional area of the gate is larger than a cross-sectional area of the channel layer, the source, and the drain combined. | 08-15-2013 |
20130241881 | PHOTOSENSING TRANSISTORS, METHODS OF MANUFACTURING THE SAME, AND DISPLAY PANELS EMPLOYING A PHOTOSENSING TRANSISTOR - Photosensing transistors, display panels employing a photosensing transistor, and methods of manufacturing the same, include a gate layer, a gate insulation layer on the gate layer, a channel layer on the gate insulation layer, an etch stop layer on a partial area of the channel layer, a source and a drain on the channel layer and separated from each other with the etch stop layer being interposed between the source and the drain, and a passivation layer covering the source, the drain, and the etch stop layer, wherein the source is separated from the etch stop layer. | 09-19-2013 |
20140028612 | TOUCH PANEL, TOUCH SCREEN APPARATUS, AND METHOD OF DRIVING THE TOUCH PANEL - A touch panel configured to drive a liquid crystal according to a voltage difference between first and second electrodes. The touch panel includes at least one display unit configured to generate an image voltage and apply the image voltage to the first electrode. The image voltage corresponds to image data to be displayed in response to activation of a display gate line. The touch panel further includes at least one sensing unit configured to sense, in response to activation of a sensor gate line, a voltage variation of the second electrode to determine whether a finger capacitance is generated by a physical touch on the touch panel. | 01-30-2014 |
20140085267 | HYBRID TOUCH PANEL, HYBRID TOUCH SCREEN APPARATUS, AND METHOD OF DRIVING THE HYBRID TOUCH PANEL - A touch panel includes a sensing unit having a first sub sensing unit configured to output a first sensing current in response to a voltage of a first gate line and configured to reset in response to a voltage of a second gate line the first sensing current corresponding to a first touch type, and a second sub sensing unit configured to output a second sensing current in response to a voltage of a third gate line and configured to reset in response to a voltage of a fourth gate line, the second sensing current corresponding to a second touch type which is different than the first touch type, a display unit configured to generate an image voltage corresponding to image data to be displayed, in response to at least one of the voltages of the first to fourth gate lines and liquid crystal. | 03-27-2014 |
20140133134 | COLOR OPTICAL PEN FOR ELECTRONIC PANEL - A color optical pen includes a tip unit, a pen body unit attached to the tip unit; a pressure sensor that is disposed in the tip unit and configured to sense at least contact between a display unit of a terminal device and the tip unit; a light source that is disposed in the pen body unit and is configured to output light through the tip unit, if the pressure sensor senses the contact; a color selection switch that is disposed on the pen body, the color selection switch configured to select a color in response to operation by a user; and a driver configured to drive the light source at a frequency or pattern based on operation of the color selection switch. | 05-15-2014 |
20140184570 | HYBRID SENSING TOUCHSCREEN APPARATUS AND METHOD OF DRIVING THE SAME - An touchscreen apparatus includes pixel rows including pixels configured to display an image, a touch-sensing unit configured to sense a physical touch and a light-sensing unit configured to sense incident light, the touch-sensing unit and the light-sensing unit being between two adjacent pixel rows and configured to operate based on first and second gate signals, a first sensor gate line connected to the light-sensing unit and the touch-sensing unit and configured to provide the first gate for activating the light-sensing unit and resetting the touch-sensing unit, a second sensor gate line connected to both the light-sensing unit and the touch-sensing unit and configured to provide the second gate signal for activating the touch-sensing unit and resetting the light-sensing unit, and a reset circuit configured to provide a common voltage to the pixels based on the operation of at least one of the light-sensing unit and the touch-sensing unit. | 07-03-2014 |
Patent application number | Description | Published |
20110108839 | Thin Film Transistor Substrate and Manufacturing Method Thereof - A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material. | 05-12-2011 |
20120105785 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes: a first substrate, a second substrate facing the first substrate, a liquid crystal layer interposed between the first substrate and the second substrate and including liquid crystal molecules, a gate line positioned on the first substrate, a data line positioned on the first substrate and crossing the gate line, a first thin film transistor and a second thin film transistor connected to the gate line and the data line, a third thin film transistor connected to the gate line and the second thin film transistor, a reference voltage line connected to the third thin film transistor, and a pixel electrode including a first subpixel electrode connected to the first thin film transistor and a second subpixel electrode connected to the second thin film transistor. | 05-03-2012 |
20120181539 | THIN FILM TRANSISTOR ARRAY PANEL - The present invention relates to a thin film transistor array panel including: a substrate; gate lines formed on the substrate; and a gate driver formed on the substrate to apply gate signals to the gate lines. The gate driver includes a first wire and a second wire to transmit different signals, and at least one of the first wire and the second wire includes a static electricity preventing structure to prevent static electricity from accumulating between the first wire and the second wire. | 07-19-2012 |
20130001567 | THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material. | 01-03-2013 |
20130087793 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern. | 04-11-2013 |
20130194536 | LIQUID CRYSTAL DISPLAY - A liquid crystal display is provided. A liquid crystal display includes: a first substrate; a thin film transistor disposed on the first substrate; and a first electrode disposed on the thin film transistor and connected to an output terminal of the thin film transistor, wherein the first electrode includes a first region and a second region each including a plurality of minute branches separated from each other by open parts, portions of at least two minute branches among the plurality of minute branches are connected to form a plurality of minute plate branches, and wherein the minute plate branch has a wider width than a minute branch. | 08-01-2013 |
20130342777 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a first substrate, a first gate line disposed on the first substrate, a second gate line disposed on the first substrate, a data line disposed on the first substrate, a reference voltage line disposed on the first substrate and extending substantially to be parallel to the data line, a first subpixel electrode disposed in a pixel area on the first substrate, a second subpixel electrode disposed in the pixel area on the first substrate, a first switching element connected to the first gate line, the data line and the first subpixel electrode, a second switching element connected to the first gate line, the data line and the second subpixel electrode, and a third switching element connected to the first subpixel electrode and the reference voltage line. | 12-26-2013 |
20140211103 | DISPLAY DEVICE - Touch-related information which cannot be acquired by the naked eye (dubbed here as sub-optical pattern information) has its corresponding sub-optical patterns respectively positioned within the aperture areas of respective domains such that the displayed image, as viewed from different viewing angles is not adversely affected by the embedded sub-optical patterns. One type of touch-related information which can be conveyed is that of touch location of a sub-optical pattern sensing pen positioned over one or more of the sub-optical patterns. | 07-31-2014 |
Patent application number | Description | Published |
20090043987 | Operation distribution method and system using buffer - Provided is an operation distribution method and system using a buffer. The operation distribution system includes a buffer, a first operation device performing a first operation and storing a result of the first operation performed by the first operation device in the buffer, and a second operation device performing a second operation using the result of the first operation stored in the buffer, thereby reducing the time required to perform operations. | 02-12-2009 |
20090175345 | Motion compensation method and apparatus - Provided is a motion compensation method and apparatus. The motion compensation method includes performing register setting for motion compensation of an m | 07-09-2009 |
20100135415 | Apparatus and method of lossless compression/restoration of selective image information - Disclosed are an apparatus and method of lossless compression and restoration of selective image information. The apparatus of lossless compression of selective image information may compress an uncompressed block image of image information without loss to convert the uncompressed block image into a compressed block image, and store the converted compressed block image. | 06-03-2010 |
20100146223 | Apparatus and method for data management - Provided is a data processing method that may transmit, from a host unit including at least one host to a tiling unit, an input parameter and first data, tile the first data using a predetermined block interleaving scheme to convert the first data to second data, and store the converted second data in a memory unit. The data processing method may transmit, from a host unit including at least one host to an inverse tiling unit, an input parameter and a request signal for first data, extract second data corresponding to the request signal from the memory unit to store at least one second data that is tiled using a predetermined block interleaving scheme, and may transmit, to the host unit, the first data that is converted by inverse tiling the second data. Here, the first data may be in a data structure of a sequential scanning scheme. | 06-10-2010 |
20100153645 | Cache control apparatus and method - A cache control apparatus and method are provided. The cache control apparatus may include a parameter input unit to receive a first parameter corresponding to a block-level cache in a main memory, a cache index extraction unit to extract a cache index from the first parameter, a cache tag extraction unit to extract a cache tag from the first parameter, and a comparison unit to determine whether a cache hit occurs using the cache index and the cache tag. | 06-17-2010 |
20110247006 | Apparatus and method of dynamically distributing load in multiple cores - Provided is an apparatus and method of dynamically distributing load occurring in multiple cores that may determine a corresponding core to perform functions constituting an application program, thereby enhancing the entire processing rate. | 10-06-2011 |
20120027314 | Apparatus for dividing image data and encoding and decoding image data in parallel, and operating method of the same - An apparatus and a method for dividing image data into partition slices and encoding and decoding the image data based on a correlation between macroblocks are provided. The macroblocks may be decoded in parallel and thus, it is possible to improve an overall image quality and processing speed. | 02-02-2012 |
20120106863 | IMAGE PROCESSING METHOD AND APPARATUS ADJUSTING PROCESSING ORDER ACCORDING TO DIRECTIVITY - An image processing apparatus may process a macro block by determining a processing order of the macro block based on a predicted directivity. The image processing apparatus may predict a directivity of the macro block based on neighboring pixel data in the macro block, determine the processing order of the macro block based on the predicted directivity, and process the macro block according to the determined processing order, thereby enhancing a data compression rate. | 05-03-2012 |
20120121196 | Apparatus for decoding image data based on availability of reference data and method thereof - An image data decoding apparatus and method are based on an availability of reference data. The image data decoding apparatus may include a core to process decoding of image data, and an availability determining device to receive, from the core, availability verification request information with respect to a reference area of a first frame included in the image data, to determine an availability with respect to the reference area based on the received availability verification request information, and to transmit, to the core, the determined availability. When the reference area is available, the core may process decoding of a second frame based on the reference area. | 05-17-2012 |
20120124324 | METHOD AND APPARATUS FOR TRANSLATING MEMORY ACCESS ADDRESS - A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks. | 05-17-2012 |
20130064463 | METHOD AND APPARATUS FOR RESTORING IMAGE BY COPYING MEMORY - A method and apparatus for restoring an image by copying a memory may include determining whether to perform an interpolation operation based on block information, and restoring a current image using a reference image depending on whether to perform the interpolation operation. | 03-14-2013 |
20130202048 | DEBLOCKING FILTERING APPARATUS AND METHOD BASED ON RASTER SCANNING - A deblocking filtering apparatus and method based on raster scanning is provided. The deblocking filtering apparatus may include a boundary determining unit to determine whether at least one of a vertical edge boundary and a horizontal edge boundary of a block corresponds to at least one of a coding unit (CU) boundary, a transform unit (TU) boundary, and a prediction unit (PU) boundary, a boundary strength (BS) computing unit to compute a BS value for at least one of the vertical edge boundary and the horizontal edge boundary when at least one of the vertical edge boundary and the horizontal edge boundary of the block corresponds to at least one of the CU boundary, the TU boundary, and the PU boundary as a result of the determining, and a filtering performing unit to perform deblocking filtering on at least one of the vertical edge boundary and the horizontal edge boundary. | 08-08-2013 |
20130215976 | ENCODING/DECODING APPARATUS AND METHOD FOR PARALLEL CORRECTION OF IN-LOOP PIXELS BASED ON MEASURED COMPLEXITY, USING VIDEO PARAMETER - An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity. | 08-22-2013 |
20140146873 | IMAGE PROCESSING APPARATUS AND METHOD - A method and apparatus for applying a tile size adaptively based on a size of a coding unit. An image processing apparatus may detect a size of a largest coding unit (LCU) used in encoding of a video from a header of a bitstream, may determine a tile size adaptively based on the detected size of the LCU, and may decode the bitstream in units of the LCU based on the determined tile size. | 05-29-2014 |
20140286391 | SAMPLE ADAPTIVE OFFSET (SAO) PROCESSING APPARATUS REUSING INPUT BUFFER AND OPERATION METHOD OF THE SAO PROCESSING APPARATUS - A sample adaptive offset (SAO) processing apparatus reusing an input buffer and an operation method of the SAO processing apparatus may include a SAO parameter parser to parse SAO parameter information from a bitstream; a SAO parameter adjuster to extract SAO type information and offset information from the parsed SAO parameter information; and a filtering performer to perform filtering on the bitstream based on the SAO type information and the offset information. | 09-25-2014 |
20140286442 | APPARATUS AND METHOD FOR IN-LOOP FILTERING BASED ON LARGEST CODING UNIT FOR REDUCING EXTERNAL MEMORY ACCESS BANDWIDTH - An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering. | 09-25-2014 |
20140310720 | APPARATUS AND METHOD OF PARALLEL PROCESSING EXECUTION - An apparatus and method of parallel processing execution that executes a job through distributing the job to a plurality of calculators, based on a calculation property of the job. The apparatus for parallel processing execution may include a plurality of calculators to calculate a job configuring a plurality of tasks of a process, and a distributor to distribute the job to a plurality of calculators based on a calculation property of the job, wherein the plurality of calculators includes a first calculator to process a job through a controlled calculation, and a second calculator to process a job through a large volume calculation. | 10-16-2014 |
Patent application number | Description | Published |
20120139883 | GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node. | 06-07-2012 |
20130038587 | SCAN DRIVER, DISPLAY DEVICE INCLUDING THE SAME, AND DRIVING METHOD THEREOF - A scan driver includes stages dependently connected to each other, where each of the stages outputs a gate signal, where a first scanning start signal is input to a first stage of the stages, where a second scanning start signal is input to a last stage of the stages, where each of the first scanning start signal and the second scanning start signal has one pulse per frame, where the stages sequentially output a gate-on voltage between a time when a pulse of the first scanning start signal for a frame is input to the first stage and a time when a pulse of the second scanning start signal for the frame is input to the last stage, and where the stages output a first low voltage lower than the gate-on voltage after the pulse of the second scanning start signal for the frame is input to the last stage. | 02-14-2013 |
20140340380 | DISPLAY DEVICE AND METHOD FOR OPERATING THE DISPLAY DEVICE - A display device includes a plurality of pixels. The display device further includes a plurality of gate lines. The display device further includes a gate driver configured provide a plurality of gate signals through the plurality of gate lines to the plurality of pixels according to at least one of a discharge signal and a scanning start signal for controlling the plurality of pixels, the gate driver being configured to provide a plurality of gate-off signals through the plurality of gate lines to the plurality of pixels according to the discharge signal. The display device further includes a signal provider configured to provide the discharge signal to the gate driver when the signal provider determines that an image signal is abnormal. | 11-20-2014 |
20140340387 | SCAN DRIVER, DISPLAY DEVICE INCLUDING THE SAME, AND DRIVING METHOD THEREOF - A scan driver includes stages dependently connected to each other, where each of the stages outputs a gate signal, where a first scanning start signal is input to a first stage of the stages, where a second scanning start signal is input to a last stage of the stages, where each of the first scanning start signal and the second scanning start signal has one pulse per frame, where the stages sequentially output a gate-on voltage between a time when a pulse of the first scanning start signal for a frame is input to the first stage and a time when a pulse of the second scanning start signal for the frame is input to the last stage, and where the stages output a first low voltage lower than the gate-on voltage after the pulse of the second scanning start signal for the frame is input to the last stage. | 11-20-2014 |
Patent application number | Description | Published |
20130209848 | DEVICE FOR FOLDING ELECTRODE ASSEMBLY - Disclosed herein is a folding device to manufacture a stacked/folded type electrode assembly having unit cells sequentially stacked in a state in which a separation film is disposed between the respective unit cells, the folding device including a web supply unit to supply a web having plate-shaped unit cells arranged at a top of a separation film at predetermined intervals, a winding jig to rotate the unit cells while holding a first one of the unit cells of the web so that the unit cells are sequentially stacked in a state in which the separation film is disposed between the respective unit cells, and a rotary shaft compensation unit to compensate for the position of a rotary shaft of the winding jig in an advancing direction of the web (X-axis direction), wherein the rotary shaft compensation unit periodically changes the position of the rotary shaft to compensate for the change in X-axis velocity (Vx) of the web caused during winding of the plate-shaped unit cells, thereby uniformly maintaining tension of the web. | 08-15-2013 |
20130240323 | DEVICE FOR FOLDING ELECTRODE ASSEMBLY - Disclosed is a unit cell transfer apparatus for arranging and delivering unit cells to a folding device, which is used in a continuous process for manufacturing a stack/folding type electrode assembly having a structure of planar unit cells wound up over a separate film. | 09-19-2013 |
20130244083 | NOVEL DEVICE FOR CUTTING ELECTRODE SHEET AND SECONDARY BATTERY MANUFACTURED USING THE SAME - Disclosed is a device for cutting an electrode sheet laminate wherein two or more continuous electrode sheets, in which an electrode active material is applied to one or both surfaces thereof, are laminated, to form a plurality of unit electrode laminates from the electrode sheet laminate, the device including a cutter to cut the electrode sheet laminate at a set position and thereby form unit electrode laminates, and two or more transport grippers arranged at the front of the cutter based on a feed direction of the electrode sheet laminate, the transport grippers drawing and transporting the electrode sheet laminate by one pitch, a size corresponding to the unit electrode laminate according to operation of the cutter, wherein while one of the transport grippers draws and transports the electrode sheet laminate, the remaining transport grippers move to a position for drawing. | 09-19-2013 |
20130244093 | METHOD FOR MANUFACTURING BATTERY CELL AND BATTERY CELL MANUFACTURED USING THE SAME - Disclosed is a method for manufacturing a battery cell including an electrode assembly and electrolyte provided in a battery case composed of a laminate sheet having a resin layer and a metal layer, which includes; (a) thermally fusing and sealing the periphery of the case except for an end part thereof while the electrode assembly is mounted in the case; (b) introducing the electrolyte through the unsealed end part then sealing the same by thermal fusion; (c) charging and discharging the battery cell to activate the same; (d) puncturing the unsealed part inside the end part to form a through-hole communicating with the inside of the case; and (e) pulling top and bottom faces of the battery case in the opposite direction to each other at the unsealed part to open the same while applying vacuum pressure, to thereby remove the gas generated during activation as well as excess electrolyte. | 09-19-2013 |
20130244095 | DEGASSING METHOD OF SECONDARY BATTERY USING CENTRIFUGAL FORCE - Disclosed is a method for manufacturing a battery cell including an electrode assembly and electrolyte provided in a battery case made of a laminate sheet having a resin layer and a metal layer, which includes: (a) mounting the electrode assembly in the battery case and sealing the periphery of the battery case except for one end part thereof through thermal fusion; (b) introducing the electrolyte through the unsealed end part and sealing the end via thermal fusion; (c) charging-discharging the battery cell to activate the same; (d) transferring gas generated during activation and excess electrolyte to the foregoing end part of the battery cell by centrifugal force; and (e) removing the gas and excess electrolyte from the end part. | 09-19-2013 |
20130247637 | NOVEL DEVICE FOR NOTCHING AND SECONDARY BATTERY MANUFACTURED USING THE SAME - Disclosed is a device for notching, at an interval of a unit electrode, a continuous electrode sheet in which an electrode active material is applied to one or both surfaces thereof, to form a plurality of unit electrodes from the electrode sheet, the device including a press to press notches on the top and the bottom of the electrode sheet at a set position, and a drawing member arranged at the rear of the press based on a feed direction of the electrode sheet, the drawing member drawing and transporting the electrode sheet by one pitch, a size corresponding to the unit electrode according to operation of the press, wherein, when one of the grippers draws and transports the electrode sheet, the remaining grippers move to a position for drawing. | 09-26-2013 |
20130252069 | MANUFACTURE DEVICE OF BATTERY CELL - Disclosed herein is a battery cell manufacturing device configured to manufacture a battery cell including two or more unit cells. The battery cell manufacturing device includes a unit cell stacking unit into which unit cells are introduced from above and in which the unit cells are sequentially stacked, a wrapping unit to wrap an outside of the unit cell stack discharged from the unit cell stacking unit with a separation film, and a heating unit to thermally shrink the separation film wrapping the outside of the unit cell stack. | 09-26-2013 |
20130252072 | NOVEL DEVICE FOR NOTCHING AND SECONDARY BATTERY MANUFACTURED USING THE SAME - Disclosed is a device for notching, at an interval of a unit electrode, a continuous electrode sheet in which an electrode active material is applied to one or both surfaces thereof, to form a plurality of unit electrodes from the electrode sheet, the device including a press to press notches on the top and the bottom of the electrode sheet at a set position, and two or more grippers arranged at the rear of the press based on a feed direction of the electrode sheet, the grippers drawing and transporting the electrode sheet by one pitch, a size corresponding to the unit electrode according to operation of the press, wherein while one of the grippers draws and transports the electrode sheet, the remaining grippers move to a position for drawing. | 09-26-2013 |
20130260211 | NOVEL DEVICE FOR LAMINATING ELECTRODE ASSEMBLY AND SECONDARY BATTERY MANUFACTURED USING THE SAME - Disclosed is a device for laminating an electrode assembly including a cathode, an anode and a separator interposed therebetween laminated in this order by thermal bonding, the device including an inlet, through which a web having the cathode/separator/anode laminate structure is fed, a heater to heat the web and thereby induce thermal bonding between the cathode, the separator and the anode, an outlet through which the thermally bonded web is discharged, and a transporter to transport the web through the inlet, the heater and the outlet, wherein the transporter imparts a transport driving force to the web in a state that the transporter contacts at least one of the top and the bottom of the web and the heater directly heats a region of the transporter contacting the web and thereby transfers thermal bonding energy to the web. | 10-03-2013 |
Patent application number | Description | Published |
20100012980 | Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same - On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer. | 01-21-2010 |
20110136340 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask. | 06-09-2011 |
20120064710 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures. | 03-15-2012 |
20140061758 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures. | 03-06-2014 |
Patent application number | Description | Published |
20110104654 | PERSONAL LEARNING APPARATUS AND METHOD BASED ON WIRELESS COMMUNICATION NETWORK - A personal learning apparatus and method using a terminal which supports an electronic book function in a wireless communication network are provided. The personal learning method includes: distributing, by a master device, learning data to the terminal within a wireless communication service area; collecting, by the master device, learning results based on the learning data from the terminal provided with the learning data; and storing, by the master device, the collected learning results. | 05-05-2011 |
20110106970 | APPARATUS AND METHOD FOR SYNCHRONIZING E-BOOK CONTENT WITH VIDEO CONTENT AND SYSTEM THEREOF - A method of synchronizing a first device capable of displaying video content and including the video content, and a second device capable of displaying E-book content associated with the video content and including the E-book content. The first device is connected to the second device according to a specific protocol. In response to a specific event for the video content or the E-book content occurring in one of the first and second devices, the device in which the specific event occurs generates event information about the specific event and transmits it to the other of the first and second devices, and performs the specific event according to the event information. Upon receiving the event information, the other of the first and second devices performs the specific event according to the received event information in synchronization with the device in which the specific event occurred, using synchronization information between the video content and the E-book content. | 05-05-2011 |
20130326016 | APPARATUS AND METHOD FOR SYNCHRONIZING E-BOOK CONTENT WITH VIDEO CONTENT AND SYSTEM THEREOF - A method of synchronizing a first device capable of displaying video content and including the video content, and a second device capable of displaying E-book content associated with the video content and including the E-book content. The first device is connected to the second device according to a specific protocol. In response to a specific event for the video content or the E-book content occurring in one of the first and second devices, the device in which the specific event occurs generates event information about the specific event and transmits it to the other of the first and second devices, and performs the specific event according to the event information. Upon receiving the event information, the other of the first and second devices performs the specific event according to the received event information in synchronization with the device in which the specific event occurred, using synchronization information between the video content and the E-book content. | 12-05-2013 |
20140015829 | IMAGE DISPLAY APPARATUS AND MENU DISPLAY METHOD - An image display apparatus includes a signal processor which constructs an image frame of a 2-dimensional (2D) content or a 3-dimensional (3D) content, an output unit which outputs the constructed image frame, an interface which receives an instruction for selecting an operating mode, and a controller which controls to perform operation in any of: a single 2D mode for displaying the image frame of a first 2D content outputted from the output unit on a display; a multi 2D mode for combining respective image frames of each of a plurality of 2D contents outputted from the output unit on the display; and a 3D mode for alternatingly displaying a left-eye image frame and a right-eye image frame of a first 3D content outputted from the output unit on the display. | 01-16-2014 |
20140015941 | IMAGE DISPLAY APPARATUS, METHOD FOR DISPLAYING IMAGE AND GLASSES APPARATUS - An image display apparatus is provided. The image display apparatus includes a signal processor which composes image frames of two-dimensional (2D) content or image frames three-dimensional (3D) content; an output unit which displays an image, wherein the output unit operates in a first mode to output the 2D content so that the image frames of the 2D content composed by the signal processor are displayed and operates a second mode to output the 3D content so that the image frame of the 3D content composed by the signal processor is displayed; an interface unit which receives a mode conversion command; and a controller which controls the output unit to convert between operating in the first mode and the second mode in accordance with the mode conversion command received through the interface unit. | 01-16-2014 |
20140160354 | DISPLAY APPARATUS AND DISPLAY METHOD - A display apparatus and a display method are provided. The display apparatus includes a plurality of receivers which are configured to receive a plurality of contents of a multi-view content, a plurality of signal processors which are configured to independently convert frame rates of the plurality of contents, and an output part which is configured to alternately output the plurality of contents according to the converted frame rates. | 06-12-2014 |
20140192174 | DISPLAY APPARATUS, SHUTTER GLASSES, DISPLAY METHOD, AND METHOD FOR OPERATING GLASSES APPARATUS - A glasses apparatus is provided. The glasses apparatus includes: a first retarder which delays phases of a first image and a second image which are output from a display apparatus, a second retarder which delays the phases of the first image and the second image in a direction different from that of the first retarder, a first shutter glass and a second shutter glass which change polarization properties of the first image and the second image, optical axes of which are rotated according to whether power is supplied or not, and a controller which controls to selectively supply the power to the first shutter glass and the second shutter glass so that a user selectively views the first image and the second image. | 07-10-2014 |
Patent application number | Description | Published |
20100154869 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a photoelectric conversion device having a semiconductor substrate including a front side and back side, a protective layer formed on the front side of the semiconductor substrate, a first non-single crystalline semiconductor layer formed on the back side of the semiconductor substrate, a first conductive layer including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer, and a second conductive layer including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer. | 06-24-2010 |
20110265866 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell is provided with a hetero-junction front structure (e.g., P/N or P/I/N) and is further provided in a back portion of thereof with a passivation layer having a plurality of openings defined therethrough. A BSF-forming binder material and a back face electrode are provided contacting the back surface and are fired to thereby bind the back face electrode to the structure and to form a BSF region extending from the openings of the passivation layer. | 11-03-2011 |
20110306163 | METHOD OF FORMING ELECTRODE AND METHOD OF MANUFACTURING SOLAR CELL USING THE SAME - A method of forming an electrode, by which the resistance of the electrode can be reduced, and a method of manufacturing a solar cell using the method of forming an electrode are provided. The electrode forming method includes coating conductive paste on a substrate, forming a metal layer by drying the conductive paste or heating the same at low temperature, and annealing the metal layer by Joule heating using the metal layer by applying an electric field to the metal layer. | 12-15-2011 |
20120103407 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SOLAR CELL - An exemplary embodiment of the present invention provides a method for manufacturing a solar cell, which includes: forming a first semiconductor layer on a first surface of a light-absorbing layer, forming a second semiconductor layer on a second surface of the light-absorbing layer, forming a first transparent conductive layer having one X-ray diffraction peak on the first semiconductor layer in a first direction, forming a second transparent conductive layer having one X-ray diffraction peak on the second semiconductor layer in a second direction opposite to the first direction, forming a first electrode on the first transparent conductive layer in the first direction and forming a second electrode on the second transparent conductive layer in the second direction, in which at least one of the first transparent conductive layer and the second transparent conductive layer is formed at about 180 to about 220° C., at least one of the first transparent conductive layer and the second transparent conductive layer includes oxidized tungsten, and 2θ is 30.2±0.1 degrees in the X-ray diffraction peak. | 05-03-2012 |
20120129295 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - Disclosed herein is a photoelectric conversion device having a semiconductor substrate including a front side and back side, a protective layer formed on the front side of the semiconductor substrate, a first non-single crystalline semiconductor layer formed on the back side of the semiconductor substrate, a first conductive layer including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer, and a second conductive layer including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer. | 05-24-2012 |
Patent application number | Description | Published |
20120116622 | METHOD FOR DETERMINING OPERATING STATE OF ELEMENT OF TRANSMISSION - A method for determining an operating state of elements of a transmission may include acquiring rotational speeds of both members constituting the elements, determining whether the rotational speeds of the members may be the same, and determining that the elements may be directly connected when the rotational speeds of the members may be the same, and that the elements may be disconnected or slip when the rotational speeds of the members may be different. | 05-10-2012 |
20130150209 | Method for Diagnosing and Controlling an Unusual Hydraulic State of Hybrid Vehicle Transmission - A system and method for diagnosing and controlling an unusual hydraulic state of an electric variable transmission of a hybrid vehicle achieving multi modes including a first mode and a second mode, the method may include determining whether the first mode is converted into the second mode, determining whether a hydraulic pressure is generated in a clutch which is engaged and the generated hydraulic pressure is higher than a predetermined hydraulic pressure when the first mode is converted into the second mode, and determining that the hybrid vehicle is in an unusual condition if the hydraulic pressure is not generated in the clutch or the generated hydraulic pressure is higher than the predetermined hydraulic pressure. | 06-13-2013 |
20130156604 | HYDRAULIC PRESSURE PRODUCING SYSTEM FOR AUTOMATIC TRANSMISSION AND CONTROL METHOD THEREOF - A hydraulic pressure producing system for an automatic transmission, and a control method thereof may include a first hydraulic pump adapted to generate hydraulic pressure for shifting, a second hydraulic pump adapted to additionally generate hydraulic pressure when hydraulic pressure supplied from the first hydraulic pump is insufficient, an accumulator adapted to store hydraulic pressure excessively generated from the first hydraulic pump, and a control unit controlling the second hydraulic pump. The method may include operating the first hydraulic pump in a state of idle stop, predicting a finish point of the idle stop state, starting operation of the second hydraulic pump prior to a predetermined time from the predicted finish point, operating the second hydraulic pump with a predetermined maximum rotation speed, and operating the second hydraulic pump with a target rotation speed. | 06-20-2013 |
20140365091 | OIL PUMP SYSTEM OF HYBRID VEHICLE AND METHOD FOR CONTROLLING THE SAME - An oil pump system and method of a hybrid vehicle stably supplies an operating hydraulic pressure to an automatic transmission using only an electric oil pump. The oil pump system of the hybrid vehicle, which supplies an operating hydraulic pressure to an automatic transmission of the hybrid vehicle, includes: an automatic transmission control unit controlling operation of the automatic transmission; an electric oil pump pumping oil to generate an operating hydraulic pressure which is to be supplied to the automatic transmission; and an oil pump control unit receiving information on a state of the automatic transmission from the automatic transmission control unit and controlling operation of the electric oil pump. The operating hydraulic pressure supplied to the automatic transmission may be generated solely through the electric oil pump which is electrically operated. | 12-11-2014 |
20140371960 | DEVICE FOR CONTROLLING FAIL-SAFE OF HYBRID VEHICLE AND METHOD THEREOF - A device for controlling fail-safe of a hybrid vehicle capable of providing fail-safe running by controlling drive of an electric oil pump with a generation voltage of a hybrid starter and generator (HSG) or a drive motor when a main relay may be cutoff due to failure of a high voltage component may include a method having determining whether the hybrid vehicle proceeds to a fail-safe mode due to a main relay opened by failure of a high voltage component during running of the hybrid vehicle or not, detecting a generation voltage of an HSG or a drive motor when the proceeding to the fail-safe mode may be determined, and generating oil pressure by controlling driving of an electric oil pump according to a generation amount of the HSG or the drive motor in running in the fail-safe mode or in a stop state. | 12-18-2014 |
20150019073 | OIL PUMP SYSTEM OF HYBRID VEHICLE AND METHOD FOR CONTROLLING THE SAME - An oil pump system of a hybrid vehicle may include an electric oil pump which supplies operating hydraulic pressure to the transmission based on a speed command; a data detector which detects data for controlling the electric oil pump; and a controller which sets a driving mode of the electric oil pump based on the data detected by the data detector, determines a basic flow rate of the set driving mode, determines a final flow rate by compensating for the basic flow rate, and applies the speed command to the electric oil pump, in which the operating hydraulic pressure is supplied to the transmission only by the electric oil pump, and the speed command is determined based on target hydraulic pressure, an oil temperature, and the final flow rate. | 01-15-2015 |
Patent application number | Description | Published |
20130182928 | METHOD AND APPARATUS FOR CORRECTING POSITRON EMISSION TOMOGRAPHY IMAGE - An image correction method includes detecting signals emitted from a tracer introduced into a target; intermittently extracting some of the detected signals according to a code string in which different codes are arranged; generating an image of the target using the extracted signals; and correcting the generated image based on at least one characteristic of the generated image. | 07-18-2013 |
20130294670 | APPARATUS AND METHOD FOR GENERATING IMAGE IN POSITRON EMISSION TOMOGRAPHY - A method and apparatus generate an image in positron emission tomography (PET). The method and apparatus are configured to divide detected signals into sections at time intervals. The detected signals are emitted from tracers introduced into a target. The method and apparatus are also configured to generate unit signals for each of the sections by accumulating the divided signals at each respective section. The method and apparatus are further configured to classify the unit signals into groups based on characteristics of each of the unit signals, and generate the medical image of the target from the unit signals classified into the groups. | 11-07-2013 |
20140050380 | APPARATUS AND METHOD FOR GENERATING MEDICAL IMAGE USING LINEAR GAMMA RAY SOURCE - Methods and apparatuses for generating a blur model of a detector, and methods and apparatus for generating a medical image are provided. A method of generating a blur model of a detector may involve: changing locations of linear gamma ray sources along at least one line and obtaining signals emitted from the linear gamma ray sources; obtaining a point spread function (PSF) with respect to at least one voxel included in the at least one line; and generating a blur model of the detector from the PSF. | 02-20-2014 |
20140056499 | APPARATUS AND METHOD FOR GENERATING IMAGE USING CORRECTION MODEL - A method and apparatus for generating an image with a correction model are provided. The method of generating a correction model of a detector may involve: changing a location of a point source and obtaining a signal emitted from the point source; calculating at least one parameter representing a distribution characteristic of the obtained signal with respect to a plurality of projection directions at each of the changed locations; and generating the correction model of the detector based on the at least one parameter. | 02-27-2014 |
20140093134 | METHOD AND APPARATUS FOR GENERATING IMAGE - A method and an apparatus for generating images are provided. The method includes generating a first sinogram for a state of an object from among states of the object based on a motion of the object, and a second sinogram for the states, based on data obtained from the object, and determining a region of interest (ROI) of the object based on the first sinogram. The method further includes extracting, from the second sinogram, third sinograms corresponding to the ROI, and estimating motion information of the ROI based on the third sinograms. The method further includes correcting the data based on the motion information. | 04-03-2014 |
20140093151 | METHODS AND APPARATUSES FOR GENERATING A RESPONSE OF A SCANNER IN AN IMAGING APPARATUS AND MEDICAL IMAGE USING THE SAME - A method of generating a response from a scanner in an imaging apparatus, a method of generating a medical image, an apparatus configured to generate a response of a scanner, and an apparatus configured to generate a medical image are provided. The method of generating a response of a scanner includes: generating point spread functions (PSFs) for the amount of the acquired signal from a point source; and generating the response of the scanner for the amount of the signal acquired, based on the PSF. | 04-03-2014 |
20140133707 | MOTION INFORMATION ESTIMATION METHOD AND IMAGE GENERATION APPARATUS USING THE SAME - A motion information estimation method and an image generation apparatus are provided. The image generation apparatus may include an image data obtaining unit for obtaining image data of the anatomic features of a subject. The image generation apparatus may also include a region-of-interest (ROI) determining unit for determining a ROI in the image data, where motion is generated in the ROI corresponding to motion of the subject. The apparatus may also include a sinogram generating unit for generating first sinograms corresponding to a plurality of states of the ROI from data obtained from the subject during a first time. Additionally, the apparatus may include an extracting unit for extracting feature values of the subject from the first sinograms, respectively, and a motion information estimating unit for estimating motion information of the subject by referring to the feature values of the subject with respect to the plurality of states. | 05-15-2014 |
20140142892 | METHOD AND APPARATUS FOR ESTIMATING POSITION DISTRIBUTION OF RADIATION EMISSION - A method and apparatus for estimating a position distribution of radiation emission The method and apparatus include obtaining a time difference between radiations detected by a pair of detectors, and creating a probability distribution function (PDF) indicating the probability of where the radiations actually were or may have been emitted. The PDF may be created based on the time difference and timing resolutions of the pair of detectors. | 05-22-2014 |
20140161335 | METHOD AND APPARATUS FOR GENERATING SYSTEM RESPONSE OF SCANNER OF IMAGING APPARATUS - A method and apparatus for generating a system response of a scanner of an imaging apparatus includes generating the system response based on a signal emitted from a point source located in a scanning space of the scanner, setting components that are factors affecting the system response, generating a component response based on a signal received from the scanner with respect to each of the components, and adjusting the system response by using the component responses. | 06-12-2014 |
20140185898 | IMAGE GENERATION METHOD AND APPARATUS - An image generation method includes classifying data according to a motion period of an object; generating respective sinograms from the classified data; updating an intermediate sinogram for an intermediate image using the sinograms; generating an updated intermediate image by performing a back projection on the updated intermediate sinogram; and generating an image in which a motion of the object is compensated by sequentially applying the sinograms in a process of generating the updated intermediate image. | 07-03-2014 |
20140221814 | MAGNETIC RESONANCE IMAGING AND POSITRON EMISSION TOMOGRAPHY SYSTEM - Provided is a magnetic resonance imaging and positron emission tomography (MRI-PET) system. The MRI-PET system includes a PET unit and a radiofrequency (RF) coil disposed within a gradient coil assembly. | 08-07-2014 |
Patent application number | Description | Published |
20120112156 | Non-Volatile Memory Devices Having Resistance Changeable Elements And Related Systems And Methods - A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed. | 05-10-2012 |
20130005096 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region. | 01-03-2013 |
20140027824 | SEMICONDUCTOR DEVICES (as amended) - In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics. | 01-30-2014 |
20150008452 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region. | 01-08-2015 |
20150035023 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed. | 02-05-2015 |
Patent application number | Description | Published |
20100202211 | NONVOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME - Provided are a nonvolatile memory device and a method for programming the same. The method for programming the nonvolatile memory device includes programming at least one memory cell of the nonvolatile memory device by repeating program loops. A first self-boosting method is applied to at least one of the program loops and a second self-boosting method, different from the first self-boosting method, is applied to at least one other of the program loops. | 08-12-2010 |
20120314500 | NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation. | 12-13-2012 |
20140376312 | NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation. | 12-25-2014 |