Patent application number | Description | Published |
20080263255 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20080263391 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
20090024772 | OVERLAYED SEPARATE DMA MAPPING OF ADAPTERS - DMA mapping for adapters configured to communicated with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of another group are overlayed in the DMA mapping space for control information for the respective adapters. | 01-22-2009 |
20090024823 | OVERLAYED SEPARATE DMA MAPPING OF ADAPTERS - DMA mapping for adapters configured to communicate with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of the another group are overlayed in the DMA mapping space for control information for the respective adapters. | 01-22-2009 |
20090119547 | SYSTEM AND ARTICLE OF MANUFACTURE FOR HANDLING A FABRIC FAILURE - Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device. | 05-07-2009 |
20090187786 | PARITY DATA MANAGEMENT SYSTEM APPARATUS AND METHOD - An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing device. The apparatus also updates the redundant disk array with the write data in accordance with a parity control map and restores the RAID controller parity map from the parity control structure as part of a data recovery operation if updating the redundant disk array with the write data is interrupted by a RAID controller failure resulting in a loss of the RAID controller parity map. In certain embodiments, the parity control structure is a RAID controller parity map. | 07-23-2009 |
20110087837 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein. | 04-14-2011 |
20110197046 | STORAGE APPLICATION PERFORMANCE MATCHING - A method for matching storage application performance in a multiple tier storage system is disclosed. Input/output (I/O) activity in the multiple tier storage system is monitored to collect statistical information. The statistical information is recurrently transformed into an exponential moving average (EMA) of the I/O activity having a predefined smoothing factor. Data portions in the multiple tier storage system are sorted into buckets of varying temperatures corresponding to the EMA. At least one data migration plan is recurrently generated for matching the sorted data portions to at least one of an available plurality of storage device classes. One data portion sorted into a higher temperature bucket is matched with a higher performance storage device class of the available plurality of storage device classes than another data portion sorted into a lower temperature bucket. | 08-11-2011 |
20110289487 | FRAMEWORK FOR A SOFTWARE ERROR INJECT TOOL - Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. While executing code that includes the error inject, an indication that an event has been triggered is received, conditions defined in the one or more error inject scenarios are evaluated using the error inject data structure, and, for each of the conditions that evaluates to true, one or more actions defined in the error inject script for the condition are performed. | 11-24-2011 |
20120191904 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein. | 07-26-2012 |
20120215949 | STORAGE APPLICATION PERFORMANCE MATCHING - Input/output (I/O) activity in the multiple tier storage system is monitored to collect statistical information. The statistical information is recurrently transformed into an exponential moving average (EMA) of the I/O activity having a predefined smoothing factor. Data portions in the multiple tier storage system are sorted into buckets of varying temperatures corresponding to the EMA. At least one data migration plan is recurrently generated for matching the sorted data portions to at least one of an available plurality of storage device classes. One data portion sorted into a higher temperature bucket is matched with a higher performance storage device class of the available plurality of storage device classes than another data portion sorted into a lower temperature bucket. | 08-23-2012 |
20120222012 | FRAMEWORK FOR A SOFTWARE ERROR INJECT TOOL - Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. While executing code that includes the error inject, an indication that an event has been triggered is received, conditions defined in the one or more error inject scenarios are evaluated using the error inject data structure, and, for each of the conditions that evaluates to true, one or more actions defined in the error inject script for the condition are performed. | 08-30-2012 |
20130073900 | PERFORMANCE ENHANCEMENT TECHNIQUE FOR RAIDS UNDER REBUILD - A method for improving the performance of a RAID under rebuild is disclosed. In one embodiment, such a method includes identifying a RAID requiring rebuild, such as by identifying a RAID having one or more failed storage-drive components. The method then automatically performs the following in response to identifying the RAID: the method identifies hot extents (i.e., extents most heavily accessed) in the RAID; the method migrates the hot extents from the identified failed RAID to a normal RAID not requiring rebuild, such as to an underused RAID; and the method rebuilds the failed RAID. The migration of the hot extents will ideally occur while the RAID is being rebuilt but may also be performed prior to the rebuild process. A corresponding apparatus and computer program product are also disclosed. | 03-21-2013 |
20130185493 | MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE - Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled. | 07-18-2013 |
20130185497 | MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE - Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled. | 07-18-2013 |
20130275694 | MIGRATING THIN-PROVISIONED VOLUMES IN TIERED STORAGE ARCHITECTURES - A method for migrating volumes in a storage system includes identifying an extent of data (belonging to a volume) requiring migration from a source extent to a target extent. The method allocates a selected number of copiers to the extent of data to migrate the extent of data from the source extent to the target extent. Each copier is configured to copy a unit of data, which is a smaller division of the extent of data. The method monitors destages (i.e., writes) that occur to the source extent as the copiers migrate the extent of data from the source extent to the target extent. In the event the destages occur faster than the copiers can copy units to the target extent, the method allocates additional copiers to the extent of data to assist in migrating the extent of data. A corresponding apparatus and computer program product are also disclosed. | 10-17-2013 |
20140115567 | FRAMEWORK FOR A SOFTWARE ERROR INJECT TOOL - Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. | 04-24-2014 |
20140195857 | FRAMEWORK FOR A SOFTWARE ERROR INJECT TOOL - Provided are techniques for receiving an error inject script that describes one or more error inject scenarios that define under which conditions at least one error inject is to be executed and compiling the error inject script to output an error inject data structure. While executing code that includes the error inject, an indication that an event has been triggered is received, conditions defined in the one or more error inject scenarios are evaluated using the error inject data structure, and, for each of the conditions that evaluates to true, one or more actions defined in the error inject script for the condition are performed. | 07-10-2014 |
20140207995 | USE OF DIFFERING GRANULARITY HEAT MAPS FOR CACHING AND MIGRATION - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache. | 07-24-2014 |
20140208018 | TIERED CACHING AND MIGRATION IN DIFFERING GRANULARITIES - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to use a Solid State Drive (SSD) portion of the tiered levels of storage, clumped hot ones of the groups of data segments are migrated to use the SSD portion while using the lower-speed cache for a remaining portion of the clumped hot ones, and sparsely hot ones of the groups of data segments are migrated to use the lower-speed cache while using a lower one of the tiered levels of storage for a remaining portion of the sparsely hot ones. | 07-24-2014 |
20140208020 | USE OF DIFFERING GRANULARITY HEAT MAPS FOR CACHING AND MIGRATION - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache. | 07-24-2014 |
20150046649 | MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE - Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled. | 02-12-2015 |
20150227467 | TIERED CACHING AND MIGRATION IN DIFFERING GRANULARITIES - For data processing in a computing storage environment by a processor device, the environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that clumped uniformly hot ones of the groups of data segments are migrated to use a Solid State Drive (SSD) portion of the tiered levels of storage; uniformly hot groups of data segments are determined using a first, largest granulated, heat map for a selected one of the group of the data segments; a second heat map, which is smaller than the first and having the largest granularity of the first heat map, is used to determine the clumped hot groups; and sparsely hot groups are determined when neither the first heat map nor the second heat map are hotter than the first and second predetermined thresholds, respectively. | 08-13-2015 |
Patent application number | Description | Published |
20140055163 | LOW VOLTAGE TRANSMITTER WITH VARIABLE OUTPUT SWING - Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source. | 02-27-2014 |
20140091851 | ADAPTIVE POWER GATING AND REGULATION - In one embodiment, an apparatus includes a power switch to provide a local power voltage at least one gated circuit based on a control signal. The apparatus also includes a delay sensor to provide a delay substantially equivalent to a processing delay of the at least one gated circuit. The apparatus also includes a phase detector to provide the control signal based at least in part on the delay. | 04-03-2014 |
20140093009 | DISTRIBUTED POLYPHASE FILTER - In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals. | 04-03-2014 |
20140146932 | LOW POWER DIGITAL PHASE INTERPOLATOR - Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs. | 05-29-2014 |
20140232464 | LOW POWER HIGH-SPEED DIGITAL RECEIVER - Described herein is a low power high-speed digital receiver. The apparatus of the receiver comprises: a sampling unit operable to sample a differential input signal and to boost input signal gain, the sampling unit to generate a sampled differential signal with boosted input signal gain; and a differential amplifier to amplify the sampled differential signal with boosted input signal gain, the differential amplifier to generate a differential amplified signal. | 08-21-2014 |
20150139377 | LOW POWER DIGITAL PHASE INTERPOLATOR - Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs. | 05-21-2015 |
20150222417 | LOW POWER SQUELCH CIRCUIT - Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal. | 08-06-2015 |