Son, Hwaseong-Si
Beom-Goo Son, Hwaseong-Si KR
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20120170120 | ANTI-FOG HEAT GENERATING GLASS SYSTEM AND METHOD FOR CONTROLLING THE SAME - An anti-fog heat-generating glass system, comprising: a heat-generating glass unit separating an indoor and outdoor area, including general glass and heat-generating glass; a glass surface temperature-sensing unit arranged on indoor side heat-generating glass for sensing glass surface temperature; a control unit which compares the glass surface temperature and a fogging point of the indoor area to control heat-generation of the heat-generating glass unit; and a power-source unit supplying power to the heat-generating glass system to operate the system. A method for controlling the anti-fog heat-generating glass system comprises: simultaneously sensing the temperature and relative humidity of the indoor area and the temperature of the heat-generating glass surface; calculating a fogging point based on the temperature and relative humidity of the indoor area; comparing the temperatures of the heat-generating glass surface and the fogging point; and returning to the sensing step or heating the heat-generating glass, based on the comparing step. | 07-05-2012 |
20130202821 | VACUUM GLASS PANEL AND METHOD FOR MANUFACTURING SAME - A vacuum glass panel includes patterned spacers formed by a print system using ceramic ink to enable the shapes of the patterned spacers and spacing between the patterned spacers to be uniformly controlled and to improve the speed of forming patterned spacers. The vacuum glass panel comprises: an upper glass sheet; a lower glass sheet facing the upper glass sheet; a sealing material arranged along the edges of the upper glass sheet and lower glass sheet to seal the upper glass sheet and the lower glass sheet such that a vacuum layer is formed in the space between the upper glass sheet and the lower glass sheet; and one or more patterned spacers inserted into the vacuum layer between the upper glass sheet and the lower glass sheet so as to maintain a gap having a predetermined thickness between the upper glass sheet and the lower glass sheet. | 08-08-2013 |
Byeong Seon Son, Hwaseong-Si KR
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20140062159 | HEADREST POLE GUIDE - A headrest pole guide structure may include a main body configured to be fixed to a seat back and disposed inside a seat cover, the main body having an upper surface in contact with a lower surface of the seat cover and a hollow space so that a pole may be selectively inserted into the hollow space, and a head disposed above the main body, wherein the head may be fastened to the main body with the seat cover interposed between the main body and the head. | 03-06-2014 |
20150232006 | HEATING APPARATUS FOR AUTOMOBILE SEAT AND CONTROL METHOD THEREOF - An automobile seat heating system and a method of controlling the same includes an automobile seat heating system that can supply a current only to a seat cushion heating wire until before a predetermined early-reaching temperature is reached so that a user can more quickly feel earlier heating and warm, and a method of controlling the system. | 08-20-2015 |
Byoungkeun Son, Hwaseong-Si KR
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20130329496 | NONVOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF - A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells. | 12-12-2013 |
20150348983 | SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS - A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction. | 12-03-2015 |
Chang Ho Son, Hwaseong-Si KR
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20110208369 | Demand response method, computer-readable medium and system - A demand response (DR) system, computer-readable medium and method are disclosed. The DR system controls a high-power-consumption load to be pre-operated or post-operated in a low-power-rate interval instead of a high-power-rate interval, and reduces an amount of power consumption required for a high-power-rate interval, resulting in reduction of power rates. In addition, limitation to household appliance operation is minimized, to greatly reduce inconvenience of a user. | 08-25-2011 |
20110218680 | Demand response system - A demand response (DR) system includes a DR control unit to generate different DR levels having different power rates for each power unit, and transmit a current DR level, and a household appliance to receive the DR level from the DR control unit, and differentially control energy output of a product in response to the received DR level so as to reduce power consumption of the product. As a result, the DR system reduces power consumption when power rates are high so as to reduce electricity bills. | 09-08-2011 |
20150160675 | DEMAND RESPONSE SYSTEM - A demand response (DR) system includes a DR control unit to generate different DR levels having different power rates for each power unit, and transmit a current DR level, and a household appliance to receive the DR level from the DR control unit, and differentially control energy output of a product in response to the received DR level so as to reduce power consumption of the product. As a result, the DR system reduces power consumption when power rates are high so as to reduce electricity bills. | 06-11-2015 |
Choon-Ho Son, Hwaseong-Si KR
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20160026492 | ELECTRONIC APPARATUS FOR EXECUTING VIRTUAL MACHINE AND METHOD FOR EXECUTING VIRTUAL MACHINE - A method for executing a virtual machine (VM) in an electronic device is provided. The method includes obtaining a position of a first base disk image stored in a disk image storage, creating a root disk image that backs the first base disk image based on the obtained position, and executing the VM based on the created root disk image. The method further includes, in the run-time of the VM, changing the first base disk to the second base disk, and continuing the VM based on the merged root disk. | 01-28-2016 |
Dae-Hee Son, Hwaseong-Si KR
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20140377039 | UNIT AND METHOD FOR COOLING, AND APPARATUS AND METHOD FOR TREATING SUBSTRATE - Provided is a substrate treating apparatus. The substrate treating apparatus includes an equipment front end module, a loadlock chamber, a transfer chamber, and a plurality of process chambers. The loadlock chamber includes a cooling unit for cooling a substrate treated in the process chambers, and the cooling unit includes a cooling chamber having an inner space, the cooling chamber having a gas inflow hole in one surface thereof, wherein support pins on which the substrate is placed are disposed around a circumference of the gas injection hole, a cooling gas injection part supplying a cooling gas toward the gas inflow hole, and a gas exhaust part exhausting the cooling gas supplied into the cooling chamber and fumes generated from the substrate to the outside of the cooling chamber. | 12-25-2014 |
20150311042 | SUBSTRATE TREATING APPARATUS - Provided is a substrate treating apparatus which treats a substrate using plasma. The substrate treating apparatus includes a processing chamber having an inner space in which process treatment is performed on a substrate, a cover member coupled to the processing chamber by a hinge part and rotating upwardly and downwardly with respect to the hinge part to open/close the processing chamber, and a close preventing member disposed on a sidewall of the cover member to prevent the cover member from being closed during upward rotation of the cover member. | 10-29-2015 |
Dongil Son, Hwaseong-Si KR
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20160133052 | VIRTUAL ENVIRONMENT FOR SHARING INFORMATION - An electronic device providing information through a virtual environment is disclosed. The device includes: a display; and an information providing module functionally connected with the display, wherein the information providing module displays an object corresponding to an external electronic device for the electronic device through the display, obtains information to be output through the external electronic device, and provides contents corresponding to the information in relation to a region, on which the object is displayed. | 05-12-2016 |
Dong-Il Son, Hwaseong-Si KR
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20150347080 | DATA PROCESSING METHOD AND ELECTRONIC DEVICE THEREOF - A method of operating an electronic device is provided. The method includes making a connection to another electronic device and switching to a particular mode, transmitting information on a request for switching to the particular mode to one or more wearable devices, receiving detection information from the wearable devices, and performing a function of the electronic device corresponding to the detection information. | 12-03-2015 |
Dong-Min Son, Hwaseong-Si KR
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20140261174 | APPARATUS FOR PROCESSING WAFERS - A wafer processing apparatus includes a reaction tube extending in a vertical direction, a door plate positioned under the reaction tube to seal the reaction tube. The door plate may be configured to load a boat into the reaction tube and support a plurality of wafers. The wafer processing apparatus may include a cap plate on the door plate, the cap plate including a cylindrical body. The cylindrical body may surround a lower side surface of the boat. A guiding recess may be formed in an outer surface of the cylindrical body along a circumferential direction of the cylindrical body. The wafer processing apparatus may include an exhaust portion configured to remove the first gas from the reaction tube through the guiding recess. | 09-18-2014 |
Han-Soo Son, Hwaseong-Si KR
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20150276292 | COOLING APPARATUS AND SYSTEM INCLUDING THE SAME - Cooling apparatuses and a system including the same may be provided. The cooling apparatus including a freezer, a first cooling unit configured to cool a first cooling water supplied to the freezer in open air, and a second cooling unit configured to cool a second cooling water supplied to the first cooling unit may be provided. According to a temperature difference between the open air and the first cooling water, the second cooling unit may circulate the second cooling water separately with respect to the first cooling water or mix the second cooling water into the first cooling water. | 10-01-2015 |
Ho-Shin Son, Hwaseong-Si KR
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20120066714 | IMAGE PROCESSING APPARATUS AND METHOD OF PROVIDING USER INTERFACE THEROF - An image processing apparatus includes a reception unit receiving broadcasting data, a signal processing unit which processes the received broadcasting data, a storage unit which stores the processed broadcasting data when a recording function starts, an output unit which provides a user interface, and a control unit which controls the output unit to provide the user interface that includes information on a available space of the storage unit and a record proceeding space against the available space when the recording function starts. Accordingly, convenience of a user who uses the recording function can be sought. | 03-15-2012 |
20130039635 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD FOR SEQUENTIALLY STORING DATA BASED ON A TIME SHIFT - An image processing apparatus is provided. The image processing apparatus includes a reception unit which receives broadcast data; a storage unit which, in response to a time shift function being turned on, sequentially stores broadcast data received via the reception unit; and a control unit which, in response to the storage unit being filled with a predefined amount (in time) of broadcast data, generates a file in which broadcast data is stored in time order by deleting least recent broadcast data in the storage unit while storing subsequent broadcast data to most recent broadcast data in the storage unit in a spare storage space of the storage unit next to the most recent broadcast data. | 02-14-2013 |
20150249861 | BROADCASTING SIGNAL RECEIVING APPARATUS AND CONTROL METHOD OF THE SAME - A broadcasting signal receiving apparatus a method of controlling the same are provided. The broadcasting signal receiving apparatus includes: a signal receiver configured to receive a broadcasting signal including a stream of data for displaying an image; a buffer configured to store the stream; an interface configured to interface the buffer and a storage device including a storage space for reproducing the stream; a controller configured to control the interface to receive storage information about the stream from the buffer, to receive the stream from the buffer based on the received storage information, and to store the stream in the storage device. | 09-03-2015 |
Hosung Son, Hwaseong-Si KR
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20160133728 | METHODS OF FORMING SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE - Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region. | 05-12-2016 |
Ho-Sung Son, Hwaseong-Si KR
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20140369115 | SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer. | 12-18-2014 |
20160141381 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers. | 05-19-2016 |
Hyung-Su Son, Hwaseong-Si KR
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20110097829 | METHOD FOR INSPECTION OF DEFECTS ON A SUBSTRATE - A method for inspection of defects on a substrate includes positioning a probe of a scanning probe microscopy (SPM) over and spaced apart from a substrate, includes scanning the substrate by changing a relative position of the probe with respect to the substrate on a plane spaced apart from and parallel to the substrate, and includes measuring a value of an induced current generated via the probe in at least two different regions of the substrate. The value of the induced current is variable according to at least a shape and a material of the substrate. The method further includes determining whether a defect exists by comparing the values of the induced currents measured in the at least two different regions of the substrate. | 04-28-2011 |
20160033550 | CONDUCTIVE ATOMIC FORCE MICROSCOPE AND METHOD OF OPERATING THE SAME - A conductive atomic force microscope including a plurality of probe structures each including a probe and a cantilever connected thereto, a power supplier applying a bias voltage, a current detector detecting a first current flowing between a sample object and each of the probes and a second current flowing between a measurement object and each of the probes, and calculating representative currents for the sample and measurement objects based on the first and second currents, respectively, and a controller calculating a ratio between representative currents of the sample object measured by each of the probe structures, calculating a scaling factor for scaling the representative current with respect to the measurement object measured by each of the probes, and determine a reproducible current measurement value based on the second measurement current and the scaling factor may be provided. | 02-04-2016 |
Hyun Ho Son, Hwaseong-Si KR
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20150214079 | WET STATION - There is provided a wet station including: a loading unit to and from which a front open unified pod (FOUP) in which semiconductor wafers are installed and a stocker in which dummy wafers are installed are loaded and unloaded; a wafer transferring robot removing the semiconductor wafers from the loaded FOUP and loading the semiconductor wafers into a wafer guide; a dummy transferring robot removing the dummy wafers from the loaded stocker and loading the dummy wafers into empty slots of the wafer guide in which the semiconductor wafers have not been loaded; and a processing chamber receiving the wafer guide fully loaded with the semiconductor wafers and the dummy wafers and performing a cleaning process on the semiconductor wafers. | 07-30-2015 |
Hyunjun Son, Hwaseong-Si KR
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20120073688 | AUTO TRANSMISSION HYDRAULIC PRESSURE CONTROL APPARATUS - An auto transmission hydraulic control apparatus may include six friction elements that of which two friction elements operate to achieve a corresponding to each stage by hydraulic pressure, five direct-controlled solenoid valves that individually and directly control hydraulic pressure to four friction elements and equally and directly control hydraulic pressure to the other two friction elements, an on-off solenoid valve converting output state and non-output state of hydraulic pressure, a switch valve in which one side of a valve spool is supplied by a spring to selectively supply hydraulic pressure from one of the direct-controlled solenoid valves, equally and directly controlling the hydraulic pressure supplied to the two friction element, in accordance with whether hydraulic pressure from on-off solenoid valve is applied to the other side thereof, and four fail-safe valves disposed between the direct-controlled solenoid valves and the friction elements to structurally limit available arrangements of the friction elements. | 03-29-2012 |
20130146156 | HYDRAULIC PRESSURE CONTROL SYSTEM FOR TORQUE CONVERTER - A hydraulic pressure control system for a torque converter includes a lock-up clutch operated according to pressure difference between an engagement and disengagement side oil chambers, a first hydraulic line communicated with the disengagement side oil chamber, second and third hydraulic lines communicated with the engagement side oil chamber, and a lock-up switch valve and a torque converter hydraulic pressure control valve that generate pressure difference between the second and the third hydraulic line communicated so that fluid within the engagement side oil chamber is circulated in lock-up on state of the lock-up clutch, and the lock-up switch valve and the torque converter hydraulic pressure control valve generate pressure difference between the second and the third hydraulic line in slip state of the lock-up clutch higher than the pressure difference between the second and the third hydraulic line in the lock-up on state of the lock-up clutch. | 06-13-2013 |
20140097056 | HYDRAULIC CONTROL APPARATUS FOR HYDRAULIC TORQUE CONVERTER - A hydraulic control apparatus may be provided with a lock-up clutch operated or not by hydraulic pressure difference between an engagement-side oil chamber and a disengagement-side oil chamber and may include a first hydraulic line supplying hydraulic pressure to the disengagement-side oil chamber or exhausting the hydraulic pressure from the disengagement-side oil chamber, a second hydraulic line supplying hydraulic pressure to the engagement-side oil chamber or exhausting the hydraulic pressure from the engagement-side oil chamber, and a third hydraulic line connected to a slip switch valve, and selectively exhausting through the slip switch valve the hydraulic pressure supplied to the engagement-side oil chamber. | 04-10-2014 |
Jai-Ick Son, Hwaseong-Si KR
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20100046292 | Non-volatile memory device and bad block remapping method - A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address. | 02-25-2010 |
Jong Pil Son, Hwaseong-Si KR
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20140068203 | MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF - A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address. | 03-06-2014 |
Jung Beom Son, Hwaseong-Si KR
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20120302567 | BICYCLIC HETEROARYL DERIVATIVES HAVING INHIBITORY ACTIVITY FOR PROTEIN KINASE - The present invention relates to a novel bicyclic heteroaryl derivative, a pharmaceutically acceptable salt thereof, a hydrate thereof, and a solvate thereof having an improved inhibitory activity for protein kinases, and a pharmaceutical composition for preventing or treating an abnormal cell growth disorder comprising same as an active ingredient. | 11-29-2012 |
20130053370 | THIENO[3,2-d]PYRIMIDINE DERIVATIVES HAVING INHIBITORY ACTIVITY ON PROTEIN KINASES - The present invention relates to a thieno[3,2-d]pyrimidine derivative of formula (I), or a pharmaceutically acceptable salt, hydrate or solvate thereof, which has an excellent inhibitory activity on protein kinases, and a pharmaceutical composition comprising the same is effective in preventing or treating abnormal cell growth diseases. | 02-28-2013 |
20130274268 | NEW BICYCLIC COMPOUND FOR MODULATING G PROTEIN-COUPLED RECEPTORS - The present invention relates to a bicyclic compound for modulating G protein-coupled receptors. The inventive compound provides preventing or treating a disease associated with the modulation of G protein-coupled receptors, particularly GPR119 G protein-coupled receptors. | 10-17-2013 |
20140371219 | THIENO[3,2-D]PYRIMIDINE DERIVATIVES HAVING INHIBITORY ACTIVITY FOR PROTEIN KINASES - Provided are a thieno[3,2-d]pyrimidine derivative of formula (I) or a pharmaceutically acceptable salt thereof having inhibitory activity for protein kinase, and a pharmaceutical composition comprising same for prevention and treatment of abnormal cell growth diseases. | 12-18-2014 |
Juyoun Son, Hwaseong-Si KR
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20140146522 | BACKLIGHT UNIT AND DISPLAY DEVICE HAVING THE SAME - A backlight unit includes a light source part configured to emit a light and a reflective sheet disposed under the light source part. The light source part includes a first light source block including a plurality of light sources with first distances therebetween and a second light source block including a plurality of light sources with second distances therebetween. The first distances increase or decrease as the light sources of the first light source block are closer to an end portion of the first light source block than to a center portion of the first light source block, and the second distances increase as the light sources of the second light source block axe closer to an end portion of the second light source block than to a center portion of the second light source block. | 05-29-2014 |
20150036320 | DISPLAY DEVICE - A display device includes an optical member, a display panel disposed on the optical member, and a plurality of light emitting units disposed under the optical member, the optical member comprising, a diffusion layer, and a reflectivity control layer which is disposed under the diffusion layer and reflects a light provided from the light emitting units, including a first base material, reflective materials dispersed in the first base material, a plurality of first portions corresponding to the plurality of light emitting units, and a second portion disposed adjacent to the first portions, where each of the plurality of first portions comprises a greater amount of the reflective materials than the second portion, when a first portion and a second portion represent a unit area having a predetermined size. | 02-05-2015 |
Kyunghoon Son, Hwaseong-Si KR
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20130038079 | CONNECTING STRUCTURE FOR CENTER FILLER AND QUARTER MEMBER IN VEHICLE - The connecting structure of a center filler and a quarter member of a vehicle may include a lateral junction portion formed at a front end of the quarter member, the lateral junction portion coupling with one side surface of the center filler in a direction substantially perpendicular to a longitudinal direction of the vehicle. The connection structure may further include a longitudinal coupling portion formed in the longitudinal direction of the vehicle coupled with an outer quarter member of the quarter member, a trim coupling portion substantially the same length as the longitudinal coupling portion coupled with trim, and a connection portion connecting the longitudinal coupling portion and the trim coupling portion to each other, wherein the lateral junction portion extends at a front end of the longitudinal coupling portion, and the lateral junction portion is bent substantially perpendicular to contact to the center filler. | 02-14-2013 |
20140054929 | 2-DOOR/3-DOOR TYPE VEHICLE HAVING REINFORCEMENT MEMBER AGAINST SIDE IMPACT - A 2-door or 3-door type vehicle having enhanced resistance against a side impact may comprise a reinforcement member that is configured to be inclinedly mounted at a side of the 2-door or 3-door type vehicle which is not equipped with a rear door for affixing the reinforcement member. The reinforcement member may be affixed to a center pillar and a side sill at respective opposite ends thereof. The reinforcement member may be affixed to a bulkhead which connects a side sill outer reinforce and a side sill inner reinforce of the side sill. | 02-27-2014 |
Min Son Son, Hwaseong-Si KR
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20130088409 | REFLECTOR ASSEMBLY FOR SATELLITE ANTENNA AND MANUFACTURING METHOD THEREOF - Disclosed herein is a reflector assembly for satellite antenna according to an exemplary embodiment of the present invention, including: a reflector having a parabola shape and made of a first material; and a reinforcing member disposed at an edge of the reflector in a circumferential direction of the reflector and made of a second material, wherein the reflector includes a bend part formed by bending an edge of the reflector so as to enclose the reinforcing member to couple the reinforcing member to the reflector. According to the present invention, it is to provide a reflector assembly for a satellite antenna capable of increasing rigidity of the reflector maintaining lightness and improving efficiency of manufacturing process and productivity. | 04-11-2013 |
20130307721 | POLARIZER ROTATING DEVICE FOR MULTI POLARIZED SATELLITE SIGNAL AND SATELLITE SIGNAL RECEIVING APPARATUS HAVING THE SAME - There are provided a polarizer rotating device and a satellite signal receiving apparatus having the same. The satellite signal receiving apparatus includes a feedhorn that receives a satellite signal; a low noise block down converter that processes the signal received by the feedhorn; a skew compensating device that is provided at the low noise block down converter or the feedhorn and rotates the low noise block down converter or the feedhorn to compensate for a skew angle when the satellite signal received by the feedhorn is a linearly polarized wave; a polarizer that receives a linearly polarized signal and a circularly polarized signal of the satellite signal; and a polarizer rotating device that rotates the polarizer when the satellite signal received by the polarizer is a circularly polarized wave. In such a simple structure, the linearly polarized wave and the circularly polarized wave are all received to be processed. | 11-21-2013 |
20130341483 | ANTENNA FOR SATELLITE COMMUNICATION - Disclosed is a satellite communication antenna, including a signal transmitting/receiving section for receiving signals from a satellite and transmitting the signals to the satellite; a driving section for rotating the signal transmitting/receiving section so that the signal transmitting/receiving section tracks the satellite; a main post, provided in a longitudinal direction, for supporting the driving section; and a vibration absorption section, provided to a circumference of the main post, for preventing vibrations or impacts from transferring into the signal transmitting/receiving section, thereby to attenuate vibrations or impacts acting on the signal transmitting/receiving section in up and down direction. | 12-26-2013 |
20150236397 | ANTENNA FOR SATELLITE COMMUNICATION - An antenna for satellite communication includes; a signal transmitting and receiving unit for receiving or transmitting a signal from/to the satellite; a driving unit for rotating the signal transmitting and receiving unit so as to enable the signal transmitting and receiving unit to track the satellite; an anti-vibration unit provided inside the posts for elastically supporting the signal transmitting and receiving unit or the driving unit. Therefore, by providing the anti-vibration unit inside the posts, it is possible to increase availability for a circumferential space of the posts and to simplify the structure of the anti-vibration unit. | 08-20-2015 |
20150263417 | SATELLITE ANTENNA HOUSING - A satellite antenna housing includes: a first layer; a second layer formed so as to be in contact with one side of the first layer; a third layer formed so as to be in contact with one side of the second layer and face the first layer; a fourth layer so as to be in contact with one side of the third layer and face the second layer; and a fifth layer so as to be in contact with one side of the fourth layer and face the third layer, wherein the first layer, the third layer, and the fifth layer may be formed of a material having a dielectric constant higher than that of the second layer and the fourth layer, and the second layer and the fourth layer may have a thickness greater than that of the first layer, the third layer, and the fifth layer. | 09-17-2015 |
Minyoung Son, Hwaseong-Si KR
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20150221062 | METHOD AND APPARATUS FOR PROCESSING GRAPHICS DATA - A method of processing graphics data includes obtaining at least one command for rendering the graphics data, determining, from among graphics data that is drawn in the rendering, graphics data to be used in another rendering based on the at least one obtained command, and transmitting, to a device for rendering the graphics data, a control signal to record the determined graphics data in a buffer. According to the method, the power consumed by a device using the method for rendering graphics data may be reduced. | 08-06-2015 |
20160125649 | RENDERING APPARATUS AND RENDERING METHOD - Provided are a rendering method and a rendering apparatus, which perform tile-based rendering. The rendering method includes determining a visible fragment based on a depth test with respect to fragments included in a tile, storing an identifier of a primitive corresponding to the visible fragment, and performing selective rendering on a primitives included in the tile based on the identifier of the primitive. The rendering apparatus implements such a rendering method. | 05-05-2016 |
Min Young Son, Hwaseong-Si KR
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20140019782 | APPARATUS AND METHOD FOR MANAGING POWER BASED ON DATA - Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type. | 01-16-2014 |
20140032976 | APPARATUS AND METHOD FOR DETECTING ERROR - An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set. | 01-30-2014 |
20140344602 | APPARATUS AND METHOD MANAGING POWER BASED ON DATA - A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information. | 11-20-2014 |
20150091925 | METHOD AND APPARATUS FOR CONVERTING DATA - Methods and apparatuses are provided for converting data efficiently and for converting input data by automatically calculating a size of an input buffer in accordance with information regarding input data when the input data is converted. The method of converting data may include receiving size information of an output buffer, receiving range information of input data used to calculate output data corresponding to each point within the output buffer, calculating size information of an input buffer using the size information of the output buffer and the range information of the input data, loading the input data using the size information of the input buffer, and calculating the output data using the loaded input data. | 04-02-2015 |
20150097830 | IMAGE PROCESSING APPARATUS AND METHOD - An image processing method includes: determining whether a draw command that is identical to a previous draw command is input; obtaining information about a transparency of a previous frame that is performed with the previous draw command; and performing image processing on a current frame based on the information about the transparency. | 04-09-2015 |
20150103071 | METHOD AND APPARATUS FOR RENDERING OBJECT AND RECORDING MEDIUM FOR RENDERING - Provided are graphics data rendering methods. The method includes obtaining, at a graphics data renderer, first space information of at least one object corresponding to graphics data of a first frame, determining a sampling mode of the first frame, based on the graphics data, and rendering graphics data of a second frame based on the first space information and the sampling mode of the first frame. Thus, memory space and time that are used for rendering graphics data may be reduced. | 04-16-2015 |
20150103072 | METHOD, APPARATUS, AND RECORDING MEDIUM FOR RENDERING OBJECT - Provided is a method of rendering an object. The method includes rendering extracting transparency information, at a object rendering apparatus, from a plurality of fragments, which comprise information representing at least one object in a frame, comparing depth information of at least one fragment, from among the plurality of fragments, located at a position of the frame, and determining a rendering of at least one fragment that is located in the position based on the comparison of the depth information and the transparency information. | 04-16-2015 |
20150145858 | METHOD AND APPARATUS TO PROCESS CURRENT COMMAND USING PREVIOUS COMMAND INFORMATION - Provided is a method and apparatus for processing a current command by using previous command information. The rendering method includes receiving first data corresponding to a current command that is to be rendered, determining whether to reuse a second data corresponding to a previous command that has already been processed by comparing the first data with the second data, and processing the current command, at a renderer, based on a result of the determination. | 05-28-2015 |
20150221122 | METHOD AND APPARATUS FOR RENDERING GRAPHICS DATA - Methods and apparatuses of rendering graphics data are disclosed to reduce the amount of computation to be performed in rendering the graphics data. The method of rendering graphics data includes extracting, at an extractor for rendering graphics data, an object existing at a first frame and a second frame on the basis of attribute information of the object in the first frame and attribute information the object in the second frame, comparing first viewpoint information of the object in the first frame with second viewpoint information of the object in the second frame, and acquiring geometric data of the object in a second viewpoint on the basis of geometric data of the object in a first viewpoint and the viewpoint comparison information. | 08-06-2015 |
Myoung-Su Son, Hwaseong-Si KR
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20140377950 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern. | 12-25-2014 |
20160020249 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region. | 01-21-2016 |
Seongmin Son, Hwaseong-Si KR
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20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 05-23-2013 |
20150137326 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer. | 05-21-2015 |
Seong-Min Son, Hwaseong-Si KR
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20140138819 | SEMICONDUCTOR DEVICE INCLUDING TSV AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided are a semiconductor device, a method of manufacturing the same, and a semiconductor package including the same. The semiconductor device includes: a substrate having a recess region in a predetermined portion of a back side of the substrate; a wiring part disposed on a front side of the substrate and including at least one wiring layer; an insulating layer disposed on the back side of the substrate and including a first portion filling in the recess region and a second portion covering the back side of the substrate of a non-recess region other than the recess region; and a through silicon via (TSV) provided in plurality of and penetrating the first portion to be electrically connected to the at least one wiring layer. | 05-22-2014 |
20140217559 | Semiconductor Devices Having Through Silicon Vias and Methods of Fabricating the Same - A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body. | 08-07-2014 |
20140327150 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME - A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer. | 11-06-2014 |
20150132950 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME - A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer. | 05-14-2015 |
Seong-Won Son, Hwaseong-Si KR
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20110181761 | CIRCUIT DEVICE FOR PREVENTING RADIATION EMISSION IN PORTABLE TERMINAL WITH TWO CAMERAS - A circuit device for preventing radiation emission in a portable terminal with two cameras is provided. The device includes a first camera, a second camera, a processor, and a 3-state buffer. The processor outputs a first control signal controlling an operation of the first camera and a second control signal controlling an operation of the second camera. The 3-state buffer electrically connects between the first camera and the processor, and connects or disconnects between the first camera and the processor depending on the first control signal. | 07-28-2011 |
Seung-Hyun Son, Hwaseong-Si KR
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20130002119 | FIELD EMISSION PANEL - A field emission panel is provided. The field emission panel includes a first substrate and a second substrate, a sealing member and a plurality of spaces which are disposed between the first substrate and the second substrate, a plurality of concave portions which are formed on a surface of the first substrate, a plurality of cathode electrodes which are disposed within each of the plurality of concave portions, a plurality of field emission materials which are disposed on each of the cathode electrodes, a plurality of gate electrodes which are fixed to areas of the surface of the first substrate which separate the concave portions of the first substrate with a gap therebetween, a light emission unit which is disposed on the second substrate, and a charging prevention resistance unit which is disposed on the first substrate, on a gap between a pair of gate electrodes. | 01-03-2013 |
Su Hyoung Son, Hwaseong-Si KR
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20110140127 | SEMI-CONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor light-emitting device and a method for manufacturing the same is disclosed, which improves light extraction efficiency by forming a plurality of protrusions on a surface of a substrate for growing a nitride semiconductor material thereon, the semiconductor light-emitting device comprising a substrate; one or more first protrusions on the substrate, each first protrusion having a recess through which a surface of the substrate is exposed planarly; a first semiconductor layer on the substrate including the first protrusions; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer; and a second electrode on the second semiconductor layer. | 06-16-2011 |
20120070924 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a method for manufacturing a semiconductor light-emitting device, which carries out a wet-etching process after a dry-etching process so as to form protrusions in a surface of a substrate for growing a nitride semiconductor material thereon. The method comprises coating a substrate with photoresist; forming a mask pattern on the substrate by selectively removing the photoresist; forming protrusions on the substrate by dry-etching the substrate with the mask pattern through the use of etching gas; wet-etching the dry-etched substrate through the use of etching solution; forming a first semiconductor layer on the substrate including the protrusions; forming an active layer on the first semiconductor layer; forming a second semiconductor layer on the active layer; etching predetermined portions of the active layer and second semiconductor layer until the first semiconductor layer is exposed; and forming a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer, and forming a second electrode on the second semiconductor layer. | 03-22-2012 |
20140206120 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - The disclosed light emitting diode includes a substrate provided, at a surface thereof, with protrusions, a buffer layer formed over the entirety of the surface of the substrate, a first semiconductor layer formed over the buffer layer, an active layer formed on a portion of the first semiconductor layer, a second semiconductor layer formed over the active layer, a first electrode pad formed on another portion of the first semiconductor layer, except for the portion where the active layer is formed, and a second electrode pad formed on the second semiconductor layer. Each protrusion has a side surface inclined from the surface of the substrate at a first angle, and another side surface inclined from the surface of the substrate at a second angle different from the first angle. | 07-24-2014 |
Sung Duk Son, Hwaseong-Si KR
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20130164946 | METHOD OF FORMING SILICON OXYCARBONITRIDE FILM - The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film. | 06-27-2013 |
Sung-Ho Son, Hwaseong-Si KR
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20130161722 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include a gate structure on a substrate, the gate structure including a first metal; an insulating interlayer covering the gate structure on the substrate; a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; and/or a first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern. | 06-27-2013 |
20140017863 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING METAL GATES - Methods of manufacturing a semiconductor device including metal gates are provided. The method may include forming a resistor pattern and a dummy gate electrode, which include polysilicon, and forming an impurity region adjacent to the dummy gate electrode. The method may further include replacing the dummy gate electrode with a gate electrode and then forming metal silicide patterns on the resistor pattern and the impurity region. | 01-16-2014 |
Wangik Son, Hwaseong-Si KR
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20150311595 | ANTENNA APPARATUS AND ELECTRONIC DEVICE INCLUDING THE SAME - An antenna apparatus is provided. The antenna apparatus includes a first section including at least one slit spaced apart from an outer edge of the antenna apparatus by a predetermined distance, a second section distinguished from the first section through the slit, and a feeding module for supplying a current to at least one of the first section and the second section. | 10-29-2015 |
Woong-Kyu Son, Hwaseong-Si KR
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20140037186 | METHOD OF ANALYZING PHOTOLITHOGRAPHY PROCESSES - Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph. | 02-06-2014 |
20140264052 | Apparatus and Method for Monitoring Semiconductor Fabrication Processes Using Polarized Light - The inventive concept provides apparatuses and methods for monitoring semiconductor fabrication processes in real time using polarized light. In some embodiments, the apparatus comprises a light source configured to generate light, a beam splitter configured to reflect the light toward the wafer being processed, an objective polarizer configured to polarize the light reflected toward the wafer and to allow light reflected by the wafer to pass therethrough, a blaze grating configured to separate light reflected by the wafer according to wavelength, an array detector configured to detect the separated light and an analyzer to analyze the three-dimensional profile of the structure/pattern being formed in the wafer. | 09-18-2014 |
Yang-Soo Son, Hwaseong-Si KR
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20100012980 | Contact Structures in Substrate Having Bonded Interface, Semiconductor Device Including the Same, Methods of Fabricating the Same - On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer. | 01-21-2010 |
Yeon-Ho Son, Hwaseong-Si KR
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20100315355 | ELECTRONIC DEVICE OF TOUCH INPUT TYPE - A touch input-type electronic device is disclosed. In accordance with an embodiment of the present invention, the touch input-type electronic device includes a touchscreen panel, an actuator, which vibrates the touchscreen panel, a guide unit, which supports both ends of the actuator, such that vibration of the actuator can be transferred to the touchscreen panel, and supports the touchscreen panel, and a case, which supports the guide unit. Thus, the touch input-type electronic device in accordance with the present embodiment can provide an appealing sensory feel corresponding to a position that is pressed directly by the user, by vibrating the pressed position. | 12-16-2010 |
Yong-Hoon Son, Hwaseong-Si KR
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20110147824 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel. | 06-23-2011 |
Young-Il Son, Hwaseong-Si KR
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20110090989 | APPARATUS AND METHOD FOR REMOVING DC OFFSET IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for removing a Direct Current (DC) offset at a receiving terminal in a wireless communication system are provided. In the method, a frame is divided into at least two time resource blocks. Resource allocation information is used to discriminate between at least one time resource block of a data-unmapped interval and at least one time resource block of a data-mapped interval. The DC offset is measured during the data-unmapped interval. The DC offset is compensated during the data-unmapped interval on a time resource block basis by using the measured DC offset. | 04-21-2011 |
Youngjae Son, Hwaseong-Si KR
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20110242912 | Random Access Memory Devices Having Word Line Drivers Therein That Support Variable-Frequency Clock Signals - Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit. The word line driver circuit is further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one-half period of the clock signal is less than the length of the delay provided by the first delay unit. | 10-06-2011 |
20130235684 | RANDOM ACCESS MEMORY DEVICES HAVING WORD LINE DRIVERS THEREIN THAT SUPPORT VARIABLE-FREQUENCY CLOCK SIGNALS - Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit. | 09-12-2013 |
Young-Jae Son, Hwaseong-Si KR
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20110154142 | TEST DEVICE AND SYSTEM-ON-CHIP HAVING THE SAME - A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test. | 06-23-2011 |
20130083592 | SEMICONDUCTOR DEVICE WITH COMPLEMENTARY GLOBAL BIT LINES, OPERATING METHOD, AND MEMORY SYSTEM - A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal. | 04-04-2013 |
Young Mok Son, Hwaseong-Si KR
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20090252938 | Substrate structure and method of forming the same - Provided are a substrate structure and method of forming the same. The method of forming the substrate structure may include etching a substrate to form an etched portion having a vertical surface, forming a diffusion material layer on the whole substrate or in part of the substrate; annealing the diffusion material layer to form a seed layer diffused downward toward the surface of the etched portion, and forming a metal layer on the seed layer. Accordingly, surface characteristics of the etched portion of the substrate may be enhanced by the seed layer, and therefore, a metal layer with improved adhesion and a uniform thickness may be formed on the vertical surface of the etched portion. | 10-08-2009 |
20090289542 | Electron beam focusing electrode and electron gun using the same - An electron beam focusing electrode and an electron gun using the same may include a plate having a polygonal through-hole; at least a projecting portion formed on at least one side of the through-hole. By using the electron beam focusing electrode, a spreading phenomenon of an electron beam having a rectangular cross section may be reduced. Further, the output of the electron gun may be increased, and electron beams may be easily focused. | 11-26-2009 |
20130045336 | MOLD FOR FABRICATING BARRIER RIB AND METHOD OF FABRICATING TWO-LAYERED BARRIER RIB USING SAME - The disclosed mold includes recessed parts which have a shape corresponding to embossed portions of the barrier rib to be fabricated, and protruding parts which have a shape corresponding to depressed portions of the barrier rib to be fabricated, protrude adjacent to the recessed parts, and are tapered. The protruding parts and the recessed parts are arranged at regular intervals. It is possible to simply fabricate the two-layered barrier rib for inkjet application through a single embossing process at low cost using the mold for fabricating the barrier rib of the present invention. | 02-21-2013 |
20130193340 | ELECTRON BEAM FOCUSING ELECTRODE AND ELECTRON GUN USING THE SAME - An electron beam focusing electrode and an electron gun using the same may include a plate having a polygonal through-hole; at least a projecting portion formed on at least one side of the through-hole. By using the electron beam focusing electrode, a spreading phenomenon of an electron beam having a rectangular cross section may be reduced. Further, the output of the electron gun may be increased, and electron beams may be easily focused. | 08-01-2013 |
Youngseon Son, Hwaseong-Si KR
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20130313631 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING SAME - A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P—N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type. | 11-28-2013 |
Young-Suk Son, Hwaseong-Si KR
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20080238327 | AMOLED DRIVE CIRCUIT USING TRANSIENT CURRENT FEEDBACK AND ACTIVE MATRIX DRIVING METHOD USING THE SAME - Disclosed herein is an Active Matrix Organic Light-Emitting-Diode (AMOLED) drive circuit using transient current feedback. The AMOLED drive circuit includes a current Digital-to-Analog Converter (DAC), a data line drive transistor, a constant current source, a variable current source, a differential amplifier, and a transient charging current control unit. The DAC generates current corresponding to input digital data. The data line drive transistor is configured such that the drain terminal thereof is connected to the output node of the current DAC. The constant current source is connected between the source terminal of the data line drive transistor and a ground. The variable current source is connected between both the output node of the current DAC and the drain terminal of the drive transistor, and a voltage source. The differential amplifier is configured to input the output voltage thereof to the gate terminal of the drive transistor. The transient charging current control unit is configured to increase or decrease the bias current of the variable current source depending on variation in the voltage of the output node of the current DAC. | 10-02-2008 |
Young-Woong Son, Hwaseong-Si KR
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20080296637 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern. | 12-04-2008 |
Yunghwan Son, Hwaseong-Si KR
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20160118399 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. | 04-28-2016 |