| Patent application number | Description | Published |
|---|
| 20090091037 | Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits - A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers. | 04-09-2009 |
| 20090108384 | Optoelectronic Device with Germanium Photodetector - An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature. | 04-30-2009 |
| 20090237982 | Magnetically De-Coupling Magnetic Tunnel Junctions and Bit/Word Lines for Reducing Bit Selection Errors in Spin-Momentum Transfer Switching - Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element. | 09-24-2009 |
| 20090291388 | Method for Forming a Self-Aligned Hard Mask for Contact to a Tunnel Junction - A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack. | 11-26-2009 |
| 20090294814 | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 12-03-2009 |
| 20090297091 | Techniques for Three-Dimensional Circuit Integration - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 12-03-2009 |
| 20090324162 | CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION - An optoelectronic circuit fabrication method and integrated circuit apparatus fabricated therewith. Integrated circuits are fabricated with an integral optical coupling transition to efficiently couple optical energy from an optical fiber to an integrated optical waveguide on the integrated circuit. Layers of specific materials are deposited onto a semiconductor circuit to support etching of a trench to receive an optical coupler that performs proper impedance matching between an optical fiber and an on-circuit optical waveguide that extends part way into the transition channel. A silicon based dielectric that includes at least a portion with a refractive index substantially equal to a section of the optical fiber is deposited into the etched trench to create the optical coupler. Silicon based dielectrics with graded indices are also able to be used. Chemical mechanical polishing is used finalize preparation of the optical transition and integrated circuit. | 12-31-2009 |
| 20100038736 | SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE - A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized. | 02-18-2010 |
| 20100111470 | LOW-LOSS LOW-CROSSTALK INTEGRATED DIGITAL OPTICAL SWITCH - An optical switch includes a plurality of optical interferometric structures is serially connected between at least one optical input node and two optical output nodes. A primary waveguide directly connects an optical input node and a first optical output node. A complementary waveguide, which is directly connected to a second optical output node, is evanescently coupled with the primary waveguide in a pair of optically coupled sections provided in each optical interferometric structure. Each optical interferometric structure also includes a pair of decoupled sections, which includes a primary decoupled section embedding a portion of the primary waveguide and a complementary decoupled section which includes a portion of the complementary waveguide. The complementary decoupled section is embedded in a phase tuning structure that allows modulation of the phase of the optical signal passing through. The optical switch provides less insertion loss, less crosstalk, and wider bandwidth than prior art optical switches. | 05-06-2010 |
| 20100213561 | Optoelectronic Device with Germanium Photodetector - An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature. | 08-26-2010 |
| 20110049655 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 03-03-2011 |
| 20110133281 | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 06-09-2011 |
| 20110143482 | SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE - A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized. | 06-16-2011 |
| 20110193169 | Techniques for Three-Dimensional Circuit Integration - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 08-11-2011 |
| 20120001283 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, implanting n-type ions in the Ge layer, patterning the n-type Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline n-type Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 01-05-2012 |
| 20120115251 | PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE - Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer. | 05-10-2012 |
| 20120129302 | FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS - Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector. | 05-24-2012 |
| 20120205523 | AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES - A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism. | 08-16-2012 |
| 20120288992 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 11-15-2012 |
| 20120299136 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 11-29-2012 |
| 20120326012 | AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES - A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism. | 12-27-2012 |
| 20130065349 | Deposition of Germanium Film - A method for forming a photodetector device includes forming waveguide feature on a substrate, and forming a photodetector feature including a germanium (Ge) film, the Ge film deposited on the waveguide feature using a plasma enhanced chemical vapor deposition (PECVD) process, the PECVD process having a deposition temperature from about 500° C. to about 550° C., and a deposition pressure from about 666.612 Pa to about 1066.579 Pa. | 03-14-2013 |
| 20130069183 | Method for Forming A Self-Aligned Hard Mask for Contact to a Tunnel Junction - A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack. | 03-21-2013 |
| 20130277795 | FARBRICATION OF A LOCALIZED THICK BOX WITH PLANAR OXIDE/SOI INTERFACE ON BULK SILICON SUBSTRATE FOR SILICON PHOTONICS INTEGRATION - Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate. | 10-24-2013 |
| 20130330036 | EXCITING A SELECTED MODE IN AN OPTICAL WAVEGUIDE - A method of exciting a selected light propagation mode in a device is disclosed. At least two light beams are propagated proximate a waveguide of the device substantially parallel to a selected surface of the waveguide. Light is transferred from the at least two beams of light into the waveguide through the selected surface to excite the selected light propagation mode in the waveguide. | 12-12-2013 |
| 20130330037 | EXCITING A SELECTED MODE IN AN OPTICAL WAVEGUIDE - A method of exciting a selected light propagation mode in a device is disclosed. At least two light beams are propagated proximate a waveguide of the device substantially parallel to a selected surface of the waveguide. Light is transferred from the at least two beams of light into the waveguide through the selected surface to excite the selected light propagation mode in the waveguide. | 12-12-2013 |
| 20140027826 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 01-30-2014 |
| 20140029949 | OPTICAL DE-MULTIPLEXING DEVICE - An electro-optical device includes an optical de-multiplexing portion operative to output a first optical signal having a first wavelength and a second optical signal having a second wavelength, an array of photodetectors, and a switching logic portion communicatively connected to the array of photodetectors, the switching logic portion operative to determine which photodetector of the array of photodetectors is converting the first optical signal into a first electrical signal and output the first electrical signal from a first output node associated with the first optical signal. | 01-30-2014 |
| 20140029950 | OPTICAL DE-MULTIPLEXING DEVICE - A method for controlling an output of an electro-optical de-multiplexing device, the method including identifying which photodetector of a first array of photodetectors is converting a first channel of an optical signal into a first electrical channel signal, and affecting a communicative connection between the identified photodetector of the first array of photodetectors that is converting the first channel of the optical signal into the first electrical channel signal and a first output node associated with the first electrical channel signal. | 01-30-2014 |
| 20140030835 | PHOTONIC MODULATOR WITH A SEMICONDUCTOR CONTACT - A semiconductor structure includes a photonic modulator and a field effect transistor on a same substrate. The photonic modulator includes a modulator semiconductor structure and a semiconductor contact structure employing a same semiconductor material as a gate electrode of a field effect transistor. The modulator semiconductor structure includes a lateral p-n junction, and the semiconductor contact structure includes another lateral p-n junction. To form this semiconductor structure, the modulator semiconductor structure in the shape of a waveguide and an active region of a field effect transistor region can be patterned in a semiconductor substrate. A gate dielectric layer is formed on the modulator semiconductor structure and the active region, and is subsequently removed from the modulator semiconductor structure. A semiconductor material layer is deposited, patterned, and doped with patterns to form a gate electrode for the field effect transistor and the semiconductor contact structure for the waveguide. | 01-30-2014 |
| 20140064656 | POLARIZATION DIVERSE DEMULTIPLEXING - A method for demultiplexing an optical signal includes receiving a multi polarization optical signal, separating the multi polarization optical signal into a first polarization optical signal and a second polarization optical signal, rotating a polarization of the first polarization optical signal to match a polarization of the second polarization optical signal, routing the first polarization optical signal and the second polarization optical signal to a common demultiplexing device, outputting a channel of the first polarization optical signal and the second polarization optical signal to a common photodetector. | 03-06-2014 |
| 20140064729 | POLARIZATION DIVERSE DEMULTIPLEXING - An optical demultiplexing device includes a first portion operative to receive an input optical signal having a first polarization, a second polarization and multiple channels, and split the input optical signal into a first optical signal having the first polarization and a second optical signal having the first polarization, and an optical demultiplexing portion communicatively connected to the polarization splitter portion, the optical demultiplexing portion operative to receive a combination of the first optical signal and the second optical signal, and output each channel of the first optical signal and the second optical signal to a photodetector device corresponding to each channel. | 03-06-2014 |
| 20140080268 | FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS - Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide. One or more process steps may be performed simultaneously on the CMOS devices and the photonics devices. | 03-20-2014 |
| 20140080269 | FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS - Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector. | 03-20-2014 |
| 20140091374 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 04-03-2014 |
| 20140127877 | FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX LATERAL EPITAXIAL REALIGNMENT OF DEPOSITED NON-CRYSTALLINE FILM ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION - Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized. | 05-08-2014 |
| 20140127878 | FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION - Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate. | 05-08-2014 |
| 20140134789 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 05-15-2014 |
| 20140134790 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 05-15-2014 |
| 20140185981 | SILICON PHOTONICS PHOTODETECTOR INTEGRATION - A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium. | 07-03-2014 |
| 20140191302 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip. | 07-10-2014 |
| 20140191326 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. | 07-10-2014 |
| 20140197507 | BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide. | 07-17-2014 |
| 20140209985 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 07-31-2014 |
| 20140217485 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 08-07-2014 |
| 20140268113 | SINGLE-FIBER NONCRITICAL-ALIGNMENT WAFER-SCALE OPTICAL TESTING - A method of determining a parameter of a wafer is disclosed. Light is propagated through a waveguide disposed in the wafer. A first measurement of optical power is obtained at a first optical tap coupled to the waveguide and a second measurement of optical power is obtained at a second optical tap coupled to the waveguide using a photodetector placed at a selected location with respect to the wafer. A difference in optical power is determined between the first optical tap and the second optical tap from the first measurement and the second measurement. The parameter of the wafer is determined from the determined difference in optical power. | 09-18-2014 |
| 20140268120 | SINGLE-FIBER NONCRITICAL-ALIGNMENT WAFER-SCALE OPTICAL TESTING - A method of determining a parameter of a wafer is disclosed. Light is propagated through a waveguide disposed in the wafer. A first measurement of optical power is obtained at a first optical tap coupled to the waveguide and a second measurement of optical power is obtained at a second optical tap coupled to the waveguide using a photodetector placed at a selected location with respect to the wafer. A difference in optical power is determined between the first optical tap and the second optical tap from the first measurement and the second measurement. The parameter of the wafer is determined from the determined difference in optical power. | 09-18-2014 |
| 20140312443 | BUTT-COUPLED BURIED WAVEGUIDE PHOTODETECTOR - A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide. | 10-23-2014 |
| 20150054041 | CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING - A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device. | 02-26-2015 |
