Patent application number | Description | Published |
20090002528 | HIGH DYNAMIC RANGE SENSOR WITH BLOOMING DRAIN - An image sensor has at least two photodiodes in each unit pixel. A high dynamic range is achieved by selecting different exposure times for the photodiodes. Additionally, blooming is reduced. The readout timing cycle is chosen so that the short exposure time photodiodes act as drains for excess charge overflowing from the long exposure time photodiodes. To improve draining of excess charge, the arrangement of photodiodes may be further selected so that long exposure time photodiodes are neighbored along vertical and horizontal directions by short exposure time photodiodes. A micro-lens array may also be provided in which light is preferentially coupled to the long exposure time photodiodes to improve sensitivity. | 01-01-2009 |
20090128660 | LIGHT SOURCE FREQUENCY DETECTION CIRCUIT USING BIPOLAR TRANSISTOR - An apparatus for measuring the power frequency of a light source includes a photo-sensitive transistor, a modulators and a logic unit. The photo-sensitive transistor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency. | 05-21-2009 |
20090200580 | Image sensor and pixel including a deep photodetector - What is disclosed is an apparatus comprising a transfer gate formed on a substrate and a photodiode formed in the substrate next to the transfer gate. The photodiode comprises a shallow N-type collector formed in the substrate, a deep N-type collector formed in the substrate, wherein a lateral side of the deep N-type collector extends at least under the transfer gate, and a connecting N-type collector formed in the substrate between the deep N-type collector and the shallow N-type collector, wherein the connecting implant connects the deep N-type collector and the shallow N-type collector. Also disclosed is a process comprising forming a deep N-type collector in the substrate, forming a shallow N-type collector formed in the substrate, and forming a connecting N-type collector in the substrate between the deep N-type collector and the shallow N-type collector, wherein the connecting implant connects the deep N-type collector and the shallow N-type collector. A transfer gate is formed on the substrate next to the deep photodiode, wherein a lateral side of the deep N-type collector extends at least under the transfer gate. Other embodiments are disclosed and claimed. | 08-13-2009 |
20090200588 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH LIGHT REFLECTING TRANSFER GATE - A backside illuminated imaging sensor includes a semiconductor having an imaging pixel that can include a photodiode region, an insulation layer, and a reflective layer. The photodiode is typically formed in the frontside of the semiconductor substrate. A surface shield layer can be formed on the frontside of the photodiode region. A light reflecting layer can be formed using silicided polysilicon on the frontside of the sensor. The photodiode region receives light from the back surface of the semiconductor substrate. When a portion of the received light propagates through the photodiode region to the light reflecting layer, the light reflecting layer reflects the portion of light received from the photodiode region towards the photodiode region. The silicided polysilicon light reflecting layer also forms a gate of a transistor for establishing a conductive channel between the photodiode region and a floating drain. | 08-13-2009 |
20090200590 | IMAGE SENSOR WITH LOW ELECTRICAL CROSS-TALK - An array of pixels is formed using a substrate, where each pixel has a substrate having a backside and a frontside that includes metalization layers, a photodiode formed in the substrate, frontside P-wells formed using frontside processing that are adjacent to the photosensitive region, and an N-type region formed in the substrate below the photodiode. The N-type region is formed in a region of the substrate below the photodiode and is formed at least in part in a region of the substrate that is deeper than the depth of the frontside P-wells. | 08-13-2009 |
20090200624 | Circuit and photo sensor overlap for backside illumination image sensor - A backside illuminated (“BSI”) imaging sensor pixel includes a photodiode region and pixel circuitry. The photodiode region is disposed within a semiconductor die for accumulating an image charge in response to light incident upon a backside of the BSI imaging sensor pixel. The pixel circuitry includes transistor pixel circuitry disposed within the semiconductor die between a frontside of the semiconductor die and the photodiode region. At least a portion of the pixel circuitry overlaps the photodiode region. | 08-13-2009 |
20090200625 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING DEEP LIGHT REFLECTIVE TRENCHES - An array of pixels is formed using a substrate having a frontside and a backside that is for receiving incident light. Each pixel typically includes metallization layers included in the frontside of the substrate, a photosensitive region formed in the backside of the substrate, and a trench formed around the photosensitive region in the backside of the substrate. The trench causes the incident light to be directed away from the trench and towards the photosensitive region. | 08-13-2009 |
20090201395 | BACKSIDE ILLUMINATED IMAGING SENSOR WITH REDUCED LEAKAGE PHOTODIODE - A backside illuminated imaging sensor includes a semiconductor having an imaging pixel that includes a photodiode region, an insulator, and a silicide reflective layer. The photodiode region is formed in the frontside of the semiconductor substrate. The insulation layer is formed on the backside of the semiconductor substrate. The transparent electrode formed on the backside of the insulation layer. The transparent electrode allows light to be transmitted through a back surface of the semiconductor substrate such that when the transparent electrode is biased, carriers are formed in a region in the backside of the semiconductor substrate to reduce leakage current. ARC layers can be used to increase sensitivity of the sensor to selected wavelengths of light. | 08-13-2009 |
20100164042 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH BACKSIDE DIFFUSION DOPING - Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed. | 07-01-2010 |
20100276574 | IMAGE SENSOR WITH GLOBAL SHUTTER - An image sensor includes a photodiode to accumulate an image charge and a storage transistor to store the image charge. A transfer transistor is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge to a readout node and a reset transistor is coupled to the readout node. A controller is configured to apply a negative voltage to a gate of the storage transistor before activating the gate of the storage transistor to store the image charge. | 11-04-2010 |
20100323470 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING DEEP LIGHT REFLECTIVE TRENCHES - An array of pixels is formed using a semiconductor layer having a frontside and a backside through which incident light is received. Each pixel typically includes a photosensitive region formed in the semiconductor layer and a trench formed adjacent to the photosensitive region. The trench causes the incident light to be directed away from the trench and towards the photosensitive region. | 12-23-2010 |
20110284982 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH BACKSIDE DIFFUSION DOPING - Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed. | 11-24-2011 |
20120086844 | CIRCUIT AND PHOTO SENSOR OVERLAP FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel. | 04-12-2012 |
20120153123 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, supplemental capacitance node line, and a supplemental capacitance circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells to selectively couple a supplemental capacitance to the FD nodes of the second group in response to a control signal. In various embodiments, the first and second group of pixel cells may be the same group or a different group of the pixel cells and may add a capacitive boost feature or a multi conversion gain feature. | 06-21-2012 |
20130009043 | IMAGE SENSOR HAVING SUPPLEMENTAL CAPACITIVE COUPLING NODE - An image sensor includes a pixel array, a bit line, a supplemental capacitance node line, and a control circuit. The pixel array includes a plurality of pixel cells each including a floating diffusion (“FD”) node and a photosensitive element coupled to selectively transfer image charge to the FD node. The bit line is coupled to selectively conduct image data output from a first group of the pixel cells. The supplemental capacitance node line is coupled to the FD node of a second group of the pixel cells different from the first group. The control circuit is coupled to the supplemental capacitance node line to selectively increase the potential at the FD node of each of the pixel cells of the second group by selectively asserting a FD boost signal on the supplemental capacitance node line. | 01-10-2013 |
20130056800 | Image Sensor With Reduced Noise By Blocking Nitridation Using Photoresist - An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers. | 03-07-2013 |
20130082313 | CMOS IMAGE SENSOR WITH RESET SHIELD LINE - Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node. | 04-04-2013 |
20130099296 | TRANSISTOR WITH SELF-ALIGNED CHANNEL WIDTH - A device includes a transistor including a source and a drain disposed in a substrate and a gate disposed above the substrate. The gate includes a first longitudinal member disposed above the source and the drain and running substantially parallel to a channel of the transistor. The first longitudinal member is disposed over a first junction isolation area. The gate also includes a second longitudinal member disposed above the source and the drain and running substantially parallel to the channel of the transistor. The second longitudinal member is disposed over a second junction isolation region. The gate also includes a cross member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member. The cross member is disposed above and between the source and the drain. | 04-25-2013 |
20130113969 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING IMPROVED FULL WELL CAPACITY IN AN IMAGE SENSOR PIXEL - Techniques and mechanisms for improving full well capacity for pixel structures in an image sensor. In an embodiment, a first pixel structure of the image sensor includes an implant region, where a skew of the implant region corresponds to an implant angle, and a second pixel structure of the image sensor includes a transfer gate. In another embodiment, an offset of the implant region of the first pixel structure from the transfer gate of the second pixel structure corresponds to the implant angle. | 05-09-2013 |
20130221194 | ENHANCED PIXEL CELL ARCHITECTURE FOR AN IMAGE SENSOR - A backside illuminated pixel array having a buried channel source follower of a pixel cell which is coupled to output an analog signal directly to a bitline as image data. In one embodiment, the buried channel source follower of a pixel cell is coupled to a source follower power line having a line impedance which is less than that of one or more other signal lines for operating that same pixel cell. In another embodiment, a source follower power line has a line impedance which is less than at least one of a line impedance of a transfer signal line or a line impedance of a reset signal line. | 08-29-2013 |
20130265472 | METHOD, APPARATUS AND SYSTEM FOR REDUCING PIXEL CELL NOISE - Circuitry to reduce signal noise characteristics in an image sensor. In an embodiment, a bit trace line segment is located between neighboring respective segments of a source follower power trace and an additional trace which is to remain at a first voltage level during a pixel cell readout time period. In another embodiment, for each such trace segment, a smallest separation between the trace segment and the respective neighboring other one of such trace segments is substantially equal to or less than some maximum length to provide for parasitic capacitance between the bit line trace and one or more other traces. | 10-10-2013 |
20140027827 | GROUND CONTACT STRUCTURE FOR A LOW DARK CURRENT CMOS PIXEL CELL - Pixel array structures to provide a ground contact for a CMOS pixel cell. In an embodiment, an active area of a pixel cell includes a photodiode disposed in a first portion of an active area, where a second portion of the active area extends from a side of the first portion. The second portion includes a doped region to provide a ground contact for the active area. In another embodiment, the pixel cell includes a transistor to transfer the charge from the photodiode, where a gate of the transistor is adjacent to the second portion and overlaps the side of the first portion. | 01-30-2014 |
20140063304 | IMAGE SENSOR WITH FIXED POTENTIAL OUTPUT TRANSISTOR - An image sensor pixel includes a photosensitive region and pixel circuitry. The photosensitive region accumulates an image charge in response to light incident upon the image sensor. The pixel circuitry includes a transfer-storage transistor, a charge-storage area, an output transistor, and a floating diffusion region. The transfer-storage transistor is coupled between the photosensitive region and the charge-storage area. The output transistor has a channel coupled between the charge-storage area and the floating diffusion region and has a gate tied to a fixed voltage potential. The transfer-storage transistor causes the image charge to transfer from the photosensitive region to the charge-storage area and to transfer from the charge-storage area to the floating diffusion region. | 03-06-2014 |
20140299925 | CMOS IMAGE SENSOR WITH RESET SHIELD LINE - Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node. | 10-09-2014 |
20150048427 | IMAGE SENSOR PIXEL CELL WITH SWITCHED DEEP TRENCH ISOLATION STRUCTURE - A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion. | 02-19-2015 |
20150076330 | Dual VPIN HDR Image Sensor Pexel - A CMOS photodiode device for use in a dual-sensitivity imaging pixel contains at least two areas of differential doping. Transistors are provided in electrical contact with these areas to govern operation of signals emanating from the photodiode on two channels, each associated with a different sensitivity to light. A plurality of such photodiodes may be incorporate into a shared arrangement forming a single pixel, in order to enhance the signals. | 03-19-2015 |