Patent application number | Description | Published |
20130100812 | PACKET PRIORITY IN A NETWORK PROCESSOR - In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID. | 04-25-2013 |
20130111000 | WORK REQUEST PROCESSOR | 05-02-2013 |
20150085868 | Semiconductor with Virtualized Computation and Switch Resources - A semiconductor substrate has a processor configurable to support execution of a hypervisor controlling a set of virtual machines and a physical switch configurable to establish virtual ports to the set of virtual machines. | 03-26-2015 |
20150089116 | Merged TLB Structure For Multiple Sequential Address Translations - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. | 03-26-2015 |
20150089147 | Maintenance Of Cache And Tags In A Translation Lookaside Buffer - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency. | 03-26-2015 |
20150089184 | Collapsed Address Translation With Multiple Page Sizes - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB. | 03-26-2015 |
20150100737 | Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach - According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding content loaded. A conditional storing operation is then performed, the conditional storing operation includes a compare-and-swap operation, executed by a controller associated with a second cache memory, based on the maintained copy of the content and the indication of the memory location. | 04-09-2015 |
20150205640 | WORK REQUEST PROCESSOR - A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer. | 07-23-2015 |
20150243357 | Independent Ordering of Independent Threads - In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag. | 08-27-2015 |
20150249603 | PACKET OUTPUT PROCESSING - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150249604 | PACKET SCHEDULING IN A NETWORK PROCESSOR - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150249620 | PACKET SHAPING IN A NETWORK PROCESSOR - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150253997 | Method and Apparatus for Memory Allocation in a Multi-Node System - According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet. | 09-10-2015 |
20150254104 | METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM - According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices. | 09-10-2015 |
20150254183 | INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM - A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received. | 09-10-2015 |
20150261535 | METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR - According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor. The processor causes the wide command data and the information associated with the wide command to be provided directly to a coprocessor for executing the wide command. The processor and the coprocessor may reside on a single chip device. Alternatively, the processor and the coprocessor may reside on separate chip devices in a multi-chip system. | 09-17-2015 |
Patent application number | Description | Published |
20150142977 | VIRTUALIZED NETWORK INTERFACE FOR TCP REASSEMBLY BUFFER ALLOCATION - A method and a system embodying the method for dynamically allocating context for Transmission Control Protocol (TCP) reassembly, comprising providing a fixed plurality of global common TCP contexts; reserving for each of one or more virtual network interface card(s) one or more TCP context(s) out of the fixed plurality of the global common TCP contexts; and allocating to a virtual network interface card from the one or more virtual network interface card(s) a TCP context from the reserved one or more TCP contexts when a reassemble able TCP packet is received by the virtual network interface card, is disclosed. | 05-21-2015 |
20150178195 | METHOD AND AN APPARATUS FOR MEMORY ADDRESS ALLIGNMENT - A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked address pointer determined in accordance with the applied modulo arithmetic, is disclosed. | 06-25-2015 |
20150178242 | SYSTEM AND A METHOD FOR A REMOTE DIRECT MEMORY ACCESS OVER CONVERGED ETHERNET - A method and a system embodying the method for receiving a remote direct memory access packet comprising an opaque data, a virtual address, and a payload at a virtual network interface card that generated the opaque data; reconstructing a stream identifier by separating the opaque data into an encrypted stream identifier and a first digest; decrypting the encrypted stream identifier; verifying the decrypted stream identifier using the first digest; providing the verified stream identifier to a system memory management unit; and mapping the virtual address and the provided stream identifier by the system memory management unit to a physical address, is disclosed. | 06-25-2015 |
20150180793 | METHOD AND AN APPARATUS FOR VIRTUALIZATION OF A QUALITY-OF-SERVICE - A method and a system embodying the method for virtualization of a quality of service, comprising associating a packet received at an interface with an aura via an aura identifier; determining configuration parameters for the aura; determining a pool for the aura; determining the state of the pool resources, the resources comprising a level of buffers available in the pool and a level of buffers allocated to the aura; and determining a quality of service for the packet in accordance with the determined state of the pool and the configuration parameters for the aura, is disclosed. | 06-25-2015 |
20150186306 | METHOD AND AN APPARATUS FOR CONVERTING INTERRUPTS INTO SCHEDULED EVENTS - A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the interrupt; determining properties of an interrupt work in accordance with the vector number; and scheduling the interrupt work in accordance with the properties of the interrupt work, is disclosed. | 07-02-2015 |
20150186308 | METHOD AND AN APPARATUS FOR INTERUPT COLLECTING AND REPORTING - A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt delivery information in a first structure; storing for each of the at least one interrupt at least an indicator of one or more entities to execute an interrupt handler routine in a second structure; and reporting one of the at least one interrupt to the one or more entities to execute an interrupt handler routine designated in accordance with the status indicator, the enable status, the interrupt delivery information, and the at least one indicator, is disclosed. | 07-02-2015 |
20150188816 | LOOK-ASIDE PROCESSOR UNIT WITH INTERNAL AND EXTERNAL ACCESS FOR MULTICORE PROCESSORS - A method and a system embodying the method for information lookup request processing at a look-aside processor unit comprising storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet comprises a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit comprising storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet comprises an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed. | 07-02-2015 |
20150195383 | METHODS AND SYSTEMS FOR SINGLE INSTRUCTION MULTIPLE DATA PROGRAMMABLE PACKET PARSERS - A parser for parsing network packets comprises a plurality of clusters, each cluster comprising one or more engines; a launcher configured to determine a candidate cluster of the plurality of clusters to parse a subset of a plurality of received packets; a loader configured to transmit the subset of the plurality of packets to the candidate cluster, wherein each of the one or more engines in the candidate cluster is configured to parse and derive parse results for a packet of the subset of the plurality of packets; and an unloader configured to receive from the candidate cluster the parse results for the subset of the plurality of packets and to transmit that information to a target. | 07-09-2015 |
20150195384 | PACKET PARSING ENGINE - A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet. | 07-09-2015 |
20150195385 | METHODS AND SYSTEMS FOR DISTRIBUTION OF PACKETS AMONG PARSING CLUSTERS - A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit. | 07-09-2015 |
20150195386 | METHODS AND SYSTEMS FOR RESOURCE MANAGEMENT IN A SINGLE INSTRUCTION MULTIPLE DATA PACKET PARSING CLUSTER - Methods and systems are provided for operating a SIMD packet parsing cluster, wherein the cluster includes a plurality of M packet parsing engines 1 to M, and the cluster further includes a shared memory and an instruction memory storing a plurality of instructions to be performed by each of the engines, and wherein the instructions include one or more memory accessing instructions that require accessing the shared memory. The method comprises transmitting the instructions to the engines for instructions to be executed by the engines; for each of the engines 2 to M, delaying execution of each of the memory accessing instructions by a delay time compared to a previous engine; and each one of the engines performing one of the memory accessing instructions at a time that the other engines are not performing one of the memory accessing instructions. | 07-09-2015 |
20150195387 | METHODS AND SYSTEMS FOR FLEXIBLE PACKET CLASSIFICATION - A network packet classification method comprises receiving parse information derived from parsing a field in a network packet; comparing the parse information with information in a table to derive a comparison result, wherein the table includes information for mapping the field with one or more comparison results; based on the comparison result deriving a style value for the network packet; classifying the packet based on the style value; and processing the packet based on the classification. According to some embodiments, the method further comprises deriving or receiving an initial style value for the network packet, wherein deriving the style value includes modifying the initial style value based on the comparison result. According to some embodiments, the initial style value depends on a network path through which the network packet is received. The network path may include an interface or a channel through which the network packet is received. | 07-09-2015 |
20150195388 | FLOATING MASK GENERATION FOR NETWORK PACKET FLOW - A tag mask generation method comprises receiving a section_selector flag indicating whether a tag mask for a section of a network packet is to be generated; receiving from a parser a parse information for the network packet, wherein the parse information includes a section_pointer that indicates a location of the section in the network packet; generating a pointer based on the section_pointer when the section_selector indicates that the tag mask for the section is to be generated; receiving a base mask for the section; and generating the tag mask via a shifter by shifting the base mask by the amount indicated by the pointer. The parse information may further include a section_pointer_valid flag indicating whether the section is included in the network packet, and the method may further comprise including the tag mask in a combined tag mask when the section_pointer_valid flag indicates that the section is included in the network packet. | 07-09-2015 |
20150220360 | METHOD AND AN APPARATUS FOR PRE-FETCHING AND PROCESSING WORK FOR PROCESOR CORES IN A NETWORK PROCESSOR - A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed. | 08-06-2015 |
20150220872 | METHOD AND AN APPARATUS FOR WORK PACKET QUEUING, SCHEDULING, AND ORDERING WITH CONFLICT QUEUING - A method and a system embodying the method for processing conflicting work, comprising: receiving a work request, the work request indicating one or more groups from a plurality of groups; finding work by arbitrating among a plurality of queues of the one or more groups; determining whether the found work conflicts with another work; returning the found work when the determination is negative; and adding the found work into a tag-chain when the determination is affirmative is disclosed. | 08-06-2015 |
20150222698 | METHOD AND AN APPARATUS FOR WORK REQUEST ARBITRATION IN A NETWORK PROCESSOR - A method and a system embodying the method for work request arbitration, comprising receiving a work request, the work request indicating one or more groups from a plurality of groups; determining at least one of a plurality of parameters in accordance with the received work request; determining eligibility to provide work among the one or more groups that have work in a work queue in accordance with a first set of the plurality of parameters; and selecting one of the determined eligible groups to provide the work in accordance with a second set of the plurality of parameters is disclosed. | 08-06-2015 |