| Patent application number | Description | Published |
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| 20120199660 | ADAPTIVE POWER STEALING THERMOSTAT - An electronic thermostat and associated methods are disclosed for power stealing from an HVAC triggering circuit. The methods include making voltage measurements while controlling the amount of current drawn by the power stealing circuitry so as to determine a relationship that can be used to select how much current to draw during power stealing. Through the use of the described methods, the likelihood of inadvertent switching of the HVAC function (on or off) can be significantly reduced. | 08-09-2012 |
| 20120248210 | POWER MANAGEMENT IN ENERGY BUFFERED BUILDING CONTROL UNIT - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors for receiving a plurality of HVAC control wires corresponding to an HVAC system. The thermostat also includes a thermostat processing and control circuit configured to at least partially control the operation of the HVAC system and a powering circuit coupled to the HVAC wire connectors and configured to provide an electrical load power to the thermostat processing and control circuit. The powering circuit has a power extraction circuit configured to extract electrical power from one or more of the plurality of received HVAC control wires up to a first level of electrical power, a rechargeable battery, and a power control circuit coupled to the power extraction circuit, the rechargeable battery, and the thermostat processing and control circuit. The power control circuit is configured to provide the electrical load power using power from the power extraction circuit and the rechargeable battery. | 10-04-2012 |
| 20120256009 | POWER-PRESERVING COMMUNICATIONS ARCHITECTURE WITH LONG-POLLING PERSISTENT CLOUD CHANNEL FOR WIRELESS NETWORK-CONNECTED THERMOSTAT - Provided according to one or more embodiments herein are methods, systems and related architectures for facilitating network communications between a wireless network-connected thermostat and a cloud-based management server in a manner that promotes reduced power usage and extended service life of a rechargeable battery of the thermostat, while at the same time accomplishing timely data transfer between the thermostat and the cloud-based management server for suitable and time-appropriate control of an HVAC system. The thermostat further comprises powering circuitry configured to: extract electrical power from one or more HVAC control wires in a manner that does not require a “common” wire; supply electrical power for thermostat operation; recharge the rechargeable battery (if needed) using any surplus extracted power; and discharge the rechargeable battery to assist in supplying electrical power for thermostat operation during intervals in which the extracted power alone is insufficient for thermostat operation. | 10-11-2012 |
| 20120261109 | POWER MANAGEMENT IN ENERGY BUFFERED BUILDING CONTROL UNIT - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors for receiving a plurality of HVAC control wires corresponding to an HVAC system. The thermostat also includes a thermostat processing and control circuit configured to at least partially control the operation of the HVAC system and a powering circuit coupled to the HVAC wire connectors and configured to provide an electrical load power to the thermostat processing and control circuit. The powering circuit has a power extraction circuit configured to extract electrical power from one or more of the plurality of received HVAC control wires up to a first level of electrical power, a rechargeable battery, and a power control circuit. The power control circuit is configured to provide the electrical load power using power from the power extraction circuit and the rechargeable battery. | 10-18-2012 |
| 20120267089 | POWER-PRESERVING COMMUNICATIONS ARCHITECTURE WITH LONG-POLLING PERSISTENT CLOUD CHANNEL FOR WIRELESS NETWORK-CONNECTED THERMOSTAT - Provided according to one or more embodiments herein are methods, systems and related architectures for facilitating network communications between a wireless network-connected thermostat and a cloud-based management server in a manner that promotes reduced power usage and extended service life of a rechargeable battery of the thermostat, while at the same time accomplishing timely data transfer between the thermostat and the cloud-based management server for suitable and time-appropriate control of an HVAC system. The thermostat further comprises powering circuitry configured to: extract electrical power from one or more HVAC control wires in a manner that does not require a “common” wire; supply electrical power for thermostat operation; recharge the rechargeable battery (if needed) using any surplus extracted power; and discharge the rechargeable battery to assist in supplying electrical power for thermostat operation during intervals in which the extracted power alone is insufficient for thermostat operation. | 10-25-2012 |
| 20120325919 | THERMOSTAT WITH POWER STEALING DELAY INTERVAL AT TRANSITIONS BETWEEN POWER STEALING STATES - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors including a connection to at least one call relay wire. The thermostat may also include a powering circuit, including a rechargeable battery, which is configured to provide electrical power to the thermostat by power stealing from a selected call relay wire. The power stealing may comprise an active power stealing mode, in which power is taken from the same selected call relay wire that is used to call for an HVAC function, and an inactive power stealing mode in which, in which no active call is being made. The powering circuit may be configured to substantially suspend (or at least reduce the level of) power stealing for at least a first time period following each transition of the thermostat from between operating states. | 12-27-2012 |
| 20130173064 | USER-FRIENDLY, NETWORK CONNECTED LEARNING THERMOSTAT AND RELATED SYSTEMS AND METHODS - A user-friendly, network-connected learning thermostat is described. The thermostat is made up of (1) a wall-mountable backplate that includes a low-power consuming microcontroller used for activities such as polling sensors and switching on and off the HVAC functions, and (2) separable head unit that includes a higher-power consuming microprocessor, color LCD backlit display, user input devices, and wireless communications modules. The thermostat also includes a rechargeable battery and power-stealing circuitry adapted to harvest power from HVAC triggering circuits. By maintaining the microprocessor in a “sleep” state often compared to the lower-power microcontroller, high-power consuming activities, such as learning computations, wireless network communications and interfacing with a user, can be temporarily performed by the microprocessor even though the activities use energy at a greater rate than is available from the power stealing circuitry. | 07-04-2013 |
| 20130218351 | INSTALLATION OF THERMOSTAT POWERED BY RECHARGEABLE BATTERY - A thermostat is described that includes a rechargeable battery, a graphical user interface and a wireless network communication capabilities. During installation, in cases where the rechargeable battery is below a first threshold, the installation procedure is limited so as to avoid energy intensive installation steps which may not be supported by the low battery level. An example of an installation step that is avoided due to low battery level is set up of wireless communication. According to some embodiments, if the battery level is very low during initial installation, the installation process is halted while the battery is charged. An indication such as a flashing LED may be displayed so as to indicate to the user that the battery is being charged. | 08-22-2013 |
| 20130221117 | POWER MANAGEMENT IN SINGLE CIRCUIT HVAC SYSTEMS AND IN MULTIPLE CIRCUIT HVAC SYSTEMS - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors for receiving a plurality of HVAC control wires corresponding to an HVAC system. The thermostat also includes a thermostat processing and control circuit operative to at least partially control the operation of the HVAC system and a powering circuit coupled to the HVAC wire connectors and configured to provide an electrical load power to the thermostat processing and control circuit. The thermostat includes circuitry and methods for maximizing efficiency of energy harvested from the HVAC system connected to the thermostat, and depending on which system is connected to the thermostat, different power schemes can be implemented in order to obtain power from the HVAC system. | 08-29-2013 |
| 20130313331 | THERMOSTAT WITH POWER STEALING DELAY INTERVAL AT TRANSITIONS BETWEEN POWER STEALING STATES - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors including a connection to at least one call relay wire. The thermostat may also include a powering circuit, including a rechargeable battery, which is configured to provide electrical power to the thermostat by power stealing from a selected call relay wire. The power stealing may comprise an active power stealing mode, in which power is taken from the same selected call relay wire that is used to call for an HVAC function, and an inactive power stealing mode in which, in which no active call is being made. The powering circuit may be configured to substantially suspend (or at least reduce the level of) power stealing for at least a first time period following each transition of the thermostat from between operating states. | 11-28-2013 |
| 20130328809 | ACCESSIBILITY AIDS FOR USERS OF ELECTRONIC DEVICES - A screen protector is provided with tactile aids for vision-impaired users. The screen protector can be placed on the display screen of a computing device to enhance the out-of-box experience for vision-impaired users and/or guide the user during subsequent use of the device. For example, the screen protector can be configured to be tactilely-informative about how to activate accessibility features of the device and/or how to proceed with initial set-up and configuration of the device. The screen protector may include, for example, braille instructions for activating the accessibility mode and/or a raised or embossed tactile aid that identifies the location of a UI control feature that can be engaged to initiate the accessibility mode or other desired function. Once the user has engaged the accessibility mode, the user may receive verbal instructions and cues going forward so as to allow the user to successfully use the device. | 12-12-2013 |
| 20130332827 | ACCESSIBILITY AIDS FOR USERS OF ELECTRONIC DEVICES - A simplified UI mode is provided for computing devices, where complex user interface elements are replaced with simpler ones. In one embodiment, content, functions, and/or other selectable items on the home screen or panel(s) of the device are assembled into a one-dimensional list. In some cases, the simplified UI mode can be configured to receive a parsing gesture (e.g., downward drag gesture or a three-finger tap) that causes an item of the list to be aurally presented to the user, and a selection gesture (e.g., release of the drag gesture or a two-finger tap) to select the last aurally presented item. The simplified UI mode may be used in conjunction with a screen protector configured with tactile aid(s) configured to facilitate use of the device by a vision-impaired user. In one case, one of the tactile aids of the screen protector indicates how to activate the simplified user interface mode. | 12-12-2013 |
| 20140175181 | MONITORING AND RECOVERABLE PROTECTION OF THERMOSTAT SWITCHING CIRCUITRY - A method of automated sensing of an electrical anomaly associated with a thermostat may include switching a switching circuit within the thermostat to an on state. The switching circuit may be configured to activate an HVAC function when switched to the on state. The method may also include monitoring one or more electrical properties associated with the switching circuit. The method may additionally include determining if an electrical anomaly is associated with the switching circuit based at least in part on the monitored one or more electrical properties. The method may further include switching the switching circuit to an off state if an electrical anomaly is detected. | 06-26-2014 |
| 20140346240 | THERMOSTAT WITH POWER STEALING DELAY INTERVAL AT TRANSITIONS BETWEEN POWER STEALING STATES - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors including a connection to at least one call relay wire. The thermostat may also include a powering circuit, including a rechargeable battery, which is configured to provide electrical power to the thermostat by power stealing from a selected call relay wire. The power stealing may comprise an active power stealing mode, in which power is taken from the same selected call relay wire that is used to call for an HVAC function, and an inactive power stealing mode in which, in which no active call is being made. The powering circuit may be configured to substantially suspend (or at least reduce the level of) power stealing for at least a first time period following each transition of the thermostat from between operating states. | 11-27-2014 |
| 20140358295 | POWER MANAGEMENT IN ENERGY BUFFERED BUILDING CONTROL UNIT - A thermostat includes a plurality of HVAC (heating, ventilation, and air conditioning) wire connectors for receiving a plurality of HVAC control wires corresponding to an HVAC system. The thermostat also includes a thermostat processing and control circuit configured to at least partially control the operation of the HVAC system and a powering circuit coupled to the HVAC wire connectors and configured to provide an electrical load power to the thermostat processing and control circuit. The powering circuit has a power extraction circuit configured to extract electrical power from one or more of the plurality of received HVAC control wires up to a first level of electrical power, a rechargeable battery, and a power control circuit. The power control circuit is configured to provide the electrical load power using power from the power extraction circuit and the rechargeable battery. | 12-04-2014 |
| 20150021993 | POWER MANAGEMENT IN LINE POWERED HAZARD DETECTION SYSTEMS - Hazard detection systems according to embodiments described herein are operative to provide failsafe safety detection features and user interface features using circuit topology and power budgeting methods that minimize power consumption. The safety detection features can monitor environmental conditions (e.g., smoke, heat, humidity, carbon monoxide, carbon dioxide, radon, and other noxious gasses) in the vicinity of the hazard detection system associated and alarm occupants when an environmental condition exceeds a predetermined threshold. | 01-22-2015 |
| 20150021997 | POWER GATING IN HAZARD DETECTION SYSTEMS - Hazard detection systems according to embodiments described herein are operative to provide failsafe safety detection features and user interface features using circuit topology and power budgeting methods that minimize power consumption. The safety detection features can monitor environmental conditions (e.g., smoke, heat, humidity, carbon monoxide, carbon dioxide, radon, and other noxious gasses) in the vicinity of the hazard detection system associated and alarm occupants when an environmental condition exceeds a predetermined threshold. | 01-22-2015 |
| 20150022026 | POWER QUALITY DIFFERENTIATION IN HAZARD DETECTION SYSTEMS - Hazard detection systems according to embodiments described herein are operative to provide failsafe safety detection features and user interface features using circuit topology and power budgeting methods that minimize power consumption. The safety detection features can monitor environmental conditions (e.g., smoke, heat, humidity, carbon monoxide, carbon dioxide, radon, and other noxious gasses) in the vicinity of the hazard detection system associated and alarm occupants when an environmental condition exceeds a predetermined threshold. | 01-22-2015 |
| 20150022346 | COMPONENT INTERFACING IN HAZARD SAFETY SYSTEMS - Systems and methods for interfacing a hazard detection device with a control panel system via a dongle are provided. The dongle may be configured to alternate between drawing first and second amounts of power from the control panel system in response to the hazard detection device alternating between operating in a normal mode when no hazard is detected and an alarm mode when a hazard is detected. The hazard detection device may operate independently of any characteristics of the control panel system. For example, the hazard detection device may operate without drawing any power from the control panel system. Therefore, the dongle may allow for various types of hazard detection devices to interface with a common two-line power control system. | 01-22-2015 |
| 20150022349 | BIFURCATED PROCESSOR HAZARD DETECTION SYSTEMS - Hazard detection systems according to embodiments described herein are operative to provide failsafe safety detection features and user interface features using circuit topology and power budgeting methods that minimize power consumption. The safety detection features can monitor environmental conditions (e.g., smoke, heat, humidity, carbon monoxide, carbon dioxide, radon, and other noxious gasses) in the vicinity of the hazard detection system associated and alarm occupants when an environmental condition exceeds a predetermined threshold. | 01-22-2015 |
| 20150022368 | POWER MANAGEMENT IN HAZARD DETECTION SYSTEMS - Hazard detection systems according to embodiments described herein are operative to provide failsafe safety detection features and user interface features using circuit topology and power budgeting methods that minimize power consumption. The safety detection features can monitor environmental conditions (e.g., smoke, heat, humidity, carbon monoxide, carbon dioxide, radon, and other noxious gasses) in the vicinity of the hazard detection system associated and alarm occupants when an environmental condition exceeds a predetermined threshold. | 01-22-2015 |
| 20150268674 | POWER-PRESERVING COMMUNICATIONS ARCHITECTURE WITH LONG-POLLING PERSISTENT CLOUD CHANNEL FOR WIRELESS NETWORK-CONNECTED THERMOSTAT - Methods and systems facilitate network communications between a wireless network-connected thermostat and a cloud-based management server in a manner that promotes reduced power usage and extended service life of a energy-storage device of the thermostat, while at the same time accomplishing timely data transfer between the thermostat and the cloud-based management server for suitable and time-appropriate control of an HVAC system. The thermostat further comprises powering circuitry configured to: extract electrical power from one or more HVAC control wires in a manner that does not require a “common” wire; supply electrical power for thermostat operation; recharge the energy-storage device (if needed) using any surplus extracted power; and discharge the energy-storage device to assist in supplying electrical power for thermostat operation during intervals in which the extracted power alone is insufficient for thermostat operation. | 09-24-2015 |
| Patent application number | Description | Published |
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| 20080239857 | INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT - A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits | 10-02-2008 |
| 20080239858 | INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS - A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits. | 10-02-2008 |
| 20090024789 | MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.). | 01-22-2009 |
| 20090285031 | SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT - A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface. | 11-19-2009 |
| 20100271888 | System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits - A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay. | 10-28-2010 |
| 20100281280 | Interface Circuit System And Method For Performing Power Management Operations In Conjunction With Only A Portion Of A Memory Circuit - A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits | 11-04-2010 |
| 20110095783 | PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES - Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller. | 04-28-2011 |
| 20120008436 | SIMULATING A REFRESH OPERATION LATENCY - A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component. | 01-12-2012 |
| 20120011310 | SIMULATING A MEMORY STANDARD - An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM. | 01-12-2012 |
| 20120011386 | MEMORY APPARATUS OPERABLE TO PERFORM A POWER-SAVING OPERATION - A memory apparatus includes multiple memory circuits and an interface circuit to present to a host system emulated memory circuits. The interface circuit includes a first component of a first type and a second component of a second type, the first component and the second component being operable to present a host-system interface to the host system and to present a memory-circuit interface to the plurality of memory circuits, in which there is a difference in at least one aspect between the host-system interface and the memory circuit interface. At least one of the first and second components is operable to identify one or more memory circuits that is not being accessed and to perform a power-saving operation on the one or more memory circuits identified as not being accessed, where the power-saving operation includes placing the memory circuits identified as not being accessed in a precharge power down mode. | 01-12-2012 |
| 20120042204 | MEMORY SYSTEMS AND MEMORY MODULES - One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems. | 02-16-2012 |
| 20120059976 | STORAGE ARRAY CONTROLLER FOR SOLID-STATE STORAGE DEVICES - A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently. | 03-08-2012 |
| 20120059978 | Storage array controller for flash-based storage devices - The invention is an improved storage array controller that adds a level of indirection between host system and storage array. The storage array controller controls a storage array comprising at least one solid-state storage device. The storage array controller improvements include: garbage collection, sequentialization of writes, combining of writes, aggregation of writes, increased reliability, improved performance, and addition of resources and functions to a computer system with a storage subsystem. | 03-08-2012 |
| 20120109621 | System and Method for Simulating an Aspect of a Memory Circuit - A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface. | 05-03-2012 |
| 20120124281 | APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF - An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc. | 05-17-2012 |
| 20120147684 | MEMORY REFRESH APPARATUS AND METHOD - A memory refresh apparatus and method are operable such that in response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times. | 06-14-2012 |
| 20120201088 | MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.). | 08-09-2012 |
| 20120206165 | PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES - Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller. | 08-16-2012 |
| 20120226924 | INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT - A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits. | 09-06-2012 |
| 20130007399 | ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM - A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module. | 01-03-2013 |
| 20130103377 | APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF - An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc. | 04-25-2013 |
| 20130103897 | SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS - A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. | 04-25-2013 |
| 20130132661 | METHOD AND APPARATUS FOR REFRESH MANAGEMENT OF MEMORY MODULES - One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices | 05-23-2013 |
| 20130132779 | MEMORY MODULES WITH RELIABILITY AND SERVICEABILITY FUNCTIONS - One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems. | 05-23-2013 |
| 20130188424 | SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION - A method includes: receiving first information in association with a first operation to be performed on at least one of multiple flash memory circuits; storing at least a portion of the first information; receiving second information in association with a second operation to be performed on at least one of the multiple flash memory circuits, in which the second operation is a read operation or a write operation; receiving data from the flash memory circuits based on at least the first information and storing the data in a buffer; and performing the second operation utilizing the stored portion of the first information in addition to the second information on the data in the buffer. | 07-25-2013 |
| 20130191585 | SIMULATING A MEMORY STANDARD - An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. | 07-25-2013 |
| Patent application number | Description | Published |
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| 20090216939 | Emulation of abstracted DIMMs using abstracted DRAMs - One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices. | 08-27-2009 |
| 20120102292 | MEMORY MODULE WITH MEMORY STACK AND INTERFACE WITH ENHANCED CAPABILITIES - A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. | 04-26-2012 |
| 20120124277 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-17-2012 |
| 20130103896 | MEMORY MODULE WITH MEMORY STACK AND INTERFACE WITH ENHANCED CAPABILITES - A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. | 04-25-2013 |
| 20130132645 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-23-2013 |
| 20150052253 | MULTI-SERVER FRACTIONAL SUBDOMAIN DNS PROTOCOL - The present disclosure provides a detailed description of techniques used in methods, systems, and computer program products for a multi-server fractional subdomain DNS protocol. The disclosure addresses the problem of cost-effectively scaling the number of devices securely connected to the Internet. More specifically, some claims are directed to approaches for rapidly adding device subdomains while minimizing the deployment of digital security certificates by observing a fractional subdomain specification and translation protocol, which claims advance the technical fields related to cost-effectively scaling the number of devices securely connected to the Internet, as well as advancing peripheral technical fields. Some claims improve the functioning of multiple systems within the disclosed environments. | 02-19-2015 |
| 20150052258 | DIRECT MAP PROXY SYSTEM AND PROTOCOL - The present disclosure provides a detailed description of techniques used in methods, systems, and computer program products for a direct map proxy system and protocol. The claimed embodiments address the problem of flexibly and efficiently mapping to a large number of devices connected to the Internet using domain names. More specifically, some claims are directed to approaches for receiving from a user device a first domain name, mapping it to a different second domain name associated with a target device, and using the second domain name to initiate and establish a connection between the user device and target device, which claims advance the technical fields for addressing the problem of flexibly and efficiently mapping to a large number of devices connected to the Internet using domain names, as well as advancing peripheral technical fields. | 02-19-2015 |
| 20150088982 | LOAD BALANCED INTER-DEVICE MESSAGING - The present disclosure provides a detailed description of techniques used in methods, systems, and computer program products for using multiple connection URLs to enable load balanced inter-device messaging. The claimed embodiments address the problem of cost-effectively scaling the communications with an increasing number of devices connected to the Internet. More specifically, the claimed embodiments are directed to approaches for registering a listener device (e.g., mobile phone or handset) to receive messages from one or more notification devices (e.g., web camera), selecting a notification server from multiple servers to receive each notification message (e.g., using multiple URLs) and forward the message (e.g., through a push service) to the listener device. The selection of the notification server can be based on load balancing the multiple servers. | 03-26-2015 |
| 20150113172 | DEPLOYING AND MANAGING NETWORKED DEVICES - A method, system, and computer program product for network-connected devices. | 04-23-2015 |
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| 20090012627 | Double-structured tissue implant and a method for preparation and use thereof - A double-structured tissue implant and a method for preparation and use thereof for implantation into tissue defects. The double-structured tissue implant comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. A stand alone secondary scaffold implant or unit. A process for preparation of the double-structured implant or the stand alone secondary scaffold comprising lyophilization and dehydrothermal treatment. | 01-08-2009 |
| 20090012628 | Method for use of a double-structured tissue implant for treatment of tissue defects - A method for use of a double-structured tissue implant or a secondary scaffold stand alone implant for treatment of tissue defects. The double-structured tissue implant comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. A stand alone secondary scaffold implant or unit. | 01-08-2009 |
| 20090054984 | Method For Use Of A Double-Structured Tissue Implant For Treatment Of Tissue Defects - A method for use of a double-structured tissue implant or a secondary scaffold stand alone implant for treatment of tissue defects. The double-structured tissue implant comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. A method of use of a stand alone secondary scaffold implant or unit for treatment of tissue defects. | 02-26-2009 |
| 20090069903 | Method For Improvement Of Differentiation Of Mesenchymal Stem Cells Using A Double-Structured Tissue Implant - A double-structured tissue implant (DSTI) and a method for preparation and use thereof for implantation into tissue defects. The double-structured tissue implant for differentiation, growth and transformation of cells, stem cells, mesenchymal stem cells and bone marrow stem cells. DSTI comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. | 03-12-2009 |
| 20130259910 | METHOD FOR USE OF A DOUBLE-STRUCTURED TISSUE IMPLANT FOR TREATMENT OF TISSUE DEFECTS - A method for use of a double-structured tissue implant or a secondary scaffold stand alone implant for treatment of tissue defects. The double-structured tissue implant comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. A method of use of a stand alone secondary scaffold implant or unit for treatment of tissue defects. | 10-03-2013 |
| 20130273121 | SYSTEMS FOR CARTILAGE REPAIR - Neo-cartilage constructs suitable for implantation into a joint cartilage lesion in situ and a method for repair and restoration of function of injured, traumatized, aged or diseased cartilage. The construct comprises at least chondrocytes incorporated into a support matrix processed according to the algorithm comprising variable hydrostatic or atmospheric pressure or non-pressure conditions, variable rate of perfusion, variable medium composition, variable temperature, variable cell density and variable time to which the chondrocytes are subjected. | 10-17-2013 |
| 20140193468 | METHODS FOR PREPARATION OF NEO-CARTILAGE CONSTRUCTS - The invention generally relates to systems (i.e. constructs) for repairing cartilage and methods for preparing the same that introduce a bioactive agent into a culture medium, suspension, scaffold, solution incorporated into the pores of the scaffold, or combinations thereof. The introduction of a bioactive agent promotes production of neo-cartilage (i.e. immature hyaline cartilage) in the system, both ex-vivo and in-vivo. | 07-10-2014 |
| 20140302227 | Methods of coating a construct with methylated collagen - A double-structured tissue implant and a method for preparation and use thereof for implantation into tissue defects. The double-structured tissue implant comprising a primary scaffold and a secondary scaffold consisting of a soluble collagen solution in combination with a non-ionic surfactant generated and positioned within the primary scaffold. A stand alone secondary scaffold implant or unit. A process for preparation of the double-structured implant or the stand alone secondary scaffold comprising lyophilization and dehydrothermal treatment. | 10-09-2014 |
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| 20100109047 | Multijunction rare earth solar cell - Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed. | 05-06-2010 |
| 20100116315 | Active rare earth tandem solar cell - The use of rare-earth (RE and O, N, P) based materials to transition between two different semiconductor materials and enable up and/or down conversion of incident radiation is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacing enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. | 05-13-2010 |
| 20100122720 | Passive Rare Earth Tandem Solar Cell - The use of rare-earth (RE+O, N, P) based materials to transition between two semiconductor materials is disclosed. Rare earth based oxides, nitrides and phosphides provide a wide range of lattice spacings enabling, compressive, tensile or stress-free lattice matching with Group IV, III-V, and Group II-VI compounds. Disclosed embodiments include tandem solar cells. | 05-20-2010 |
| 20120073648 | Photovoltaic conversion using rare earths plus Group IV Sensitizers - The invention relates to photovoltaic device structures of more than one layer comprising rare earth compounds and Group IV materials enabling spectral harvesting outside the conventional absorption limits for silicon. | 03-29-2012 |
| 20120085399 | REO-Ge Multi-Junction Solar Cell - The invention relates to a semiconductor based structure for a device for converting radiation to electrical energy comprising various combinations of rare-earths and Group IV, III-V, and II-VI semiconductors and alloys thereof enabling enhanced performance including high radiation conversion efficiency. | 04-12-2012 |
| 20120090672 | REO-Ge Multi-Junction Solar Cell - The invention relates to a semiconductor based structure for a device for converting radiation to electrical energy comprising various combinations of rare-earths and Group IV, III-V, and II-VI semiconductors and alloys thereof enabling enhanced performance including high radiation conversion efficiency. | 04-19-2012 |
| 20130032858 | RARE EARTH OXY-NITRIDE BUFFERED III-N ON SILICON - Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride. | 02-07-2013 |
| 20130062609 | III-N FET ON SILICON USING FIELD SUPPRESSING REO - A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide. | 03-14-2013 |
| 20130062610 | LATTICE MATCHED CRYSTALLINE REFLECTOR - A virtual substrate structure with a lattice matched crystalline reflector for a light emitting device including a single crystal rare earth oxide layer deposited on a silicon substrate and substantially crystal lattice matched to the silicon substrate. A reflective layer of single crystal electrically conductive material is deposited on the layer of single crystal rare earth oxide and a layer of single crystal semiconductor material is positioned in overlying relationship to the reflective layer and substantially crystal lattice matched to the reflective layer. A single crystal rare earth oxide layer is optionally deposited between the reflective layer and the layer of semiconductor material. | 03-14-2013 |
| 20130214282 | III-N ON SILICON USING NANO STRUCTURED INTERFACE LAYER - A method of fabricating a layer of single crystal semiconductor material on a silicon substrate including providing a crystalline silicon substrate and epitaxially depositing a nano structured interface layer on the substrate. The nano structured interface layer has a thickness up to a critical thickness. The method further includes epitaxially depositing a layer of single crystal semiconductor material in overlying relationship to the nano structured interface layer. Preferably, the method includes the nano structured interface layer being a layer of coherently strained nano dots of selected material. The critical thickness of the nano dots includes a thickness up to a thickness at which the nano dots become incoherent. | 08-22-2013 |
| 20130334536 | SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx - A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide. | 12-19-2013 |
| 20140239307 | REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE - A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material. | 08-28-2014 |
| 20150014676 | III-N MATERIAL GROWN ON REN EPITAXIAL BUFFER ON Si SUBSTRATE - A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride. | 01-15-2015 |
| 20150203990 | REN SEMICONDUCTOR LAYER EPITAXIALLY GROWN ON REAlN/REO BUFFER ON Si SUBSTRATE - Rare earth semiconductor and ferromagnetic material epitaxially grown on a silicon substrate includes a buffer of single crystal epitaxial rare earth/aluminum nitride positioned on a single crystal silicon substrate and a single crystal epitaxial rare earth oxide positioned on the single crystal epitaxial aluminum nitride. A layer of single crystal epitaxial semiconductor and ferromagnetic rare earth nitride is positioned on the buffer. A layer of III-V semiconductive material may be optionally positioned on the rare earth nitride layer. | 07-23-2015 |
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| 20140030737 | IMAGE ANALYSIS AND MEASUREMENT OF BIOLOGICAL SAMPLES - Methods, devices, systems, and apparatuses are provided for the image analysis of measurement of biological samples. | 01-30-2014 |
| 20140038206 | IMAGE ANALYSIS AND MEASUREMENT OF BIOLOGICAL SAMPLES - Methods, devices, systems, and apparatuses are provided for the image analysis of measurement of biological samples. | 02-06-2014 |
| 20140057770 | High Speed, Compact Centrifuge for Use with Small Sample Volumes - In one nonlimiting example, an automated system is provided for separating one or more components in a biological fluid, wherein the system comprises: (a) a centrifuge comprising one or more bucket configured to receive a container to effect said separating of one or more components in a fluid sample; and (b) the container, wherein the container includes one or more shaped feature that is complementary to a shaped feature of the bucket. | 02-27-2014 |
| 20140193892 | IMAGE ANALYSIS AND MEASUREMENT OF BIOLOGICAL SAMPLES - Methods, devices, apparatus, and systems are provided for image analysis. Methods of image analysis may include observation, measurement, and analysis of images of biological and other samples; devices, apparatus, and systems provided herein are useful for observation, measurement, and analysis of images of such samples. The methods, devices, apparatus, and systems disclosed herein provide advantages over other methods, devices, apparatus, and systems. | 07-10-2014 |
| 20140296089 | SYSTEMS AND METHODS FOR MULTI-ANALYSIS - Systems and methods are provided for sample processing. A device may be provided, capable of receiving the sample, and performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing multiple assays. The device may comprise one or more modules that may be capable of performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing the steps using a small volume of sample. | 10-02-2014 |
| 20140308661 | SYSTEMS AND METHODS FOR MULTI-ANALYSIS - Systems and methods are provided for sample processing. A device may be provided, capable of receiving the sample, and performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing multiple assays. The device may comprise one or more modules that may be capable of performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing the steps using a small volume of sample. | 10-16-2014 |
| 20150198465 | HIGH SPEED, COMPACT CENTRIFUGE FOR USE WITH SMALL SAMPLE VOLUMES - In one nonlimiting example, an automated system is provided for separating one or more components in a biological fluid, wherein the system comprises: (a) a centrifuge comprising one or more bucket configured to receive a container to effect said separating of one or more components in a fluid sample; and (b) the container, wherein the container includes one or more shaped feature that is complementary to a shaped feature of the bucket. | 07-16-2015 |
