Patent application number | Description | Published |
20130038368 | SEMICONDUCTOR DEVICE - A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal. | 02-14-2013 |
20130039143 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command. | 02-14-2013 |
20130076401 | INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. | 03-28-2013 |
20130078807 | WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. | 03-28-2013 |
20130082352 | STACK PACKAGE - A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. | 04-04-2013 |
20130087887 | STACK PACKAGE - A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. | 04-11-2013 |
20130093007 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region. | 04-18-2013 |
20130093484 | DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. | 04-18-2013 |
20130094285 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 04-18-2013 |
20130102106 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. | 04-25-2013 |
20130102118 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 04-25-2013 |
20130102146 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. | 04-25-2013 |
20130119464 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 05-16-2013 |
20130120042 | DELAY LOCKED LOOP - A delay locked loop includes a closed loop circuit configured to generate preliminary delay information, a control unit configured to update the preliminary delay information into delay information in response to a control signal, and a first delay unit configured to delay an input clock signal by a first delay value determined by the delay information and generate an output clock signal. | 05-16-2013 |
20130121069 | INTERNAL VOLTAGE GENERATING CIRCUIT OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD THEREOF - An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal. | 05-16-2013 |
20130121082 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program operation for the even memory cells is performed, performing a program operation on the odd memory cells coupled to the odd bit lines, and coupling the odd bit line to the page buffer based on the set coupling resistance value and performing an verification operation for verifying whether threshold voltages of the odd memory cells on which the program operation is performed are a target voltage or more. | 05-16-2013 |
20130130454 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 05-23-2013 |
20130134383 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device and a method of manufacturing the same are provided. A first portion stack having a first circuit element including at least one layer selected from at least one diode layer, at least one variable resistive layer, and interconnection layer is formed on a first substrate. A second portion stack having a second circuit element including at least the other layer selected from the at least one diode layer, the at least variable resistive layer, and the at least interconnection layer is formed on a second substrate. The first circuit element and the second circuit element are bonded together and the second substrate is removed. | 05-30-2013 |
20130134508 | SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench. | 05-30-2013 |
20130137228 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 05-30-2013 |
20130137258 | METHOD FOR FABRICATING BURIED GATES USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 05-30-2013 |
20130141998 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages. | 06-06-2013 |
20130146831 | PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES - A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer, | 06-13-2013 |
20130147060 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes and extend laterally in opposite directions so as to define a zigzag arrangement together. | 06-13-2013 |
20130147517 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal. | 06-13-2013 |
20130148449 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. | 06-13-2013 |
20130157427 | ETCHING COMPOSITION AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process. | 06-20-2013 |
20130157434 | PHASE CHANGE MEMORY APPARATUS AND FABRICATION METHOD THEREOF - A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode. | 06-20-2013 |
20130162316 | PULSE GENERATION CIRCUIT, BURST ORDER CONTROL CIRCUIT, AND DATA OUTPUT CIRCUIT - A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses. | 06-27-2013 |
20130162353 | SIGNAL AMPLIFICATION CIRCUIT - A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal. | 06-27-2013 |
20130163362 | PRECHARGE CIRCUIT AND NON-VOLATILE MEMORY DEVICE - A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the precharge unit by sensing the voltage of the precharge voltage terminal, The precharge circuit may control a precharge operation by sensing a change in the voltage level of the precharge voltage terminal. | 06-27-2013 |
20130166949 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes, a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages, an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data, a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data, and a page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array. | 06-27-2013 |
20130168634 | RESISTIVE RANDOM ACCESS MEMORY DEVICE - A resistive memory device includes a lower electrode disposed on a substrate, first and second resistance layers respectively disposed on opposite sides of the lower electrode and exhibiting resistance variation at different voltages, respectively, and an upper electrode disposed on and the first and second resistance layers. | 07-04-2013 |
20130175602 | Non-Volatile Memory Device Having Three Dimensional, Vertical Channel, Alternately Stacked Gate Electrode Structure - A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel. | 07-11-2013 |
20130175603 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 07-11-2013 |
20130176794 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage. | 07-11-2013 |
20130214389 | INTEGRATED CIRCUIT - An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip. | 08-22-2013 |
Patent application number | Description | Published |
20130064020 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 03-14-2013 |
20130077377 | SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL - A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor. | 03-28-2013 |
20130077861 | IMAGE SENSING DEVICE AND IMAGE DATA PROCESSING METHOD USING THE SAME - An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process. | 03-28-2013 |
20130088930 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address. | 04-11-2013 |
20130114359 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 05-09-2013 |
20130126956 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line, | 05-23-2013 |
20130126962 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. After spacers are formed on sidewalls of a pillar pattern and a photoresist pattern exposing an OSC formation region is formed on a semiconductor substrate including the pillar pattern and the spacer, processes for removing a spacer corresponding to the OSC formation region to form an OSC, removing the photoresist pattern, forming a bit line between the pillar patterns, an epitaxial layer on the pillar pattern, and forming a vertical gate and a storage node contact, are performed so that the OSC formation process can be simplified. In addition, the OSC formation process is performed in a state that the pillar pattern has a low height so that a failure such as a not-open failure caused in the OSC formation process can be prevented. | 05-23-2013 |
20130126964 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for forming the same are disclosed, which can greatly reduce a cell area as compared to a conventional layout of 8F2 and 6F2, and need not form a bit line contact, a storage node contact, or a land plug, such that the number of fabrication steps is reduced and a contact region between the bit line and the active region is increased in size. The semiconductor device including a vertical transistor includes an active region formed over a semiconductor substrate, a first recess formed to have a predetermined depth at both sides of the active region, and a bit line buried in the first recess. | 05-23-2013 |
20130127013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact. | 05-23-2013 |
20130134374 | VARIABLE RESISTOR, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND METHODS OF FABRICATING THE SAME - A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode. | 05-30-2013 |
20130141144 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed. | 06-06-2013 |
20130141975 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated. | 06-06-2013 |
20130141982 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period. | 06-06-2013 |
20130147995 | SIGNAL PROVIDING APPARATUS, AND ANALOG-TO-DIGITAL CONVERTING APPARATUS AND IMAGE SENSOR USING THE SAME - An image sensor includes: a plurality of image pixels providing a reset signal and a data signal; a signal providing apparatus generating a ramp signal, and sequentially providing the reset signal, the data signal, and the ramp signal; and an analog-to-digital converting apparatus converting the data signal into a digital signal by using a first timing at which the amplitude of the ramp signal is changed based on the amplitude of the reset signal and a second timing at which the amplitude of the ramp signal is changed based on the amplitude of the data signal, wherein the reset signal used to generate the ramp signal and the data signal which has been converted into the data digital signal may be output from the same image pixel. | 06-13-2013 |
20130148433 | OPERATING METHOD IN A NON-VOLATILE MEMORY DEVICE - A method of verifying a non-volatile memory device includes precharging a bit line to a high level through a sensing node by applying a first voltage to a bit line select transistor coupled between the bit line and the sensing node; applying a verifying voltage to a plurality of word lines; disconnecting the bit line from the sensing node; and coupling the bit line to the sensing node by applying a second voltage to the bit line select transistor so as to detect a level of the bit line, the second voltage being smaller than the first voltage, wherein, a difference between the first voltage and the second voltage in a verifying operation is higher than a difference between a first voltage and a second voltage that are used in a read operation. | 06-13-2013 |
20130148890 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD - A digital image processing apparatus and method are provided. The digital image processing apparatus includes: a Y component processing unit receiving a Y component and performing edge enhancement processing and first noise reduction processing on the Y component by using a memory allocated to the Y component; and a CbCr processing unit receiving a Cb component and a Cr component, and performing false color suppression processing and second noise reduction processing on the Cb component and the Cr component by using a memory allocated to the Cb component and the Cr component, where the Y component, the Cb component and the Cr component are variables of the YCbCr color space. | 06-13-2013 |
20130151176 | SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. | 06-13-2013 |
20130153990 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern. | 06-20-2013 |
20130155775 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch. | 06-20-2013 |
20130166993 | ERROR DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other. | 06-27-2013 |
20130168814 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a mesh shaped lower electrode of a peripheral region is used as a reservoir capacitor to increase the size of a region contacting a dielectric film, such that Cs deterioration is minimized. An exemplary semiconductor device may include a line-type storage node contact plug formed over a semiconductor substrate, a mesh shaped lower electrode formed over the storage node contact plug, and a dielectric film and an upper electrode formed over the lower electrode. | 07-04-2013 |
20130168875 | SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate. | 07-04-2013 |
20130178064 | POLISHING SLURRY AND CHEMICAL MECHANICAL PLANARIZATION METHOD USING THE SAME - A polishing slurry for a chemical mechanical planarization process includes polishing particles and polyhedral nanoscale particles having a smaller size than the polishing particles and including a bond of silicon (Si) and oxygen (O). | 07-11-2013 |
20130189608 | EXTREME ULTRA VIOLET (EUV) MASK - An extreme ultra violate (EUV) mask is disclosed, which prevents defects from shot overlap encountered in wafer exposure as well as reflection of unnecessary EUV and DUV generated in a black border region, such that a pattern CD is reduced and defects are not created. The EUV mask includes a quartz substrate, a multi-layered reflection film formed over the quartz substrate to reflect exposure light, an absorption layer formed over the multi-layered reflection film, a black border region formed over the quartz substrate that does not include the multi-layered reflection film, and a blind layer formed in a position including at least one of over the absorption layer, over the quartz substrate, and below the quartz substrate. | 07-25-2013 |
20130196256 | REFLECTION-TYPE PHOTOMASKS AND METHODS OF FABRICATING THE SAME - Reflection-type photomasks are provided. The reflection-type photomask includes a substrate and a reflection layer on a front surface of the substrate. The substrate includes a pattern transfer region, a light blocking region and a border region. A trench penetrates the reflection layer in the border region to expose the substrate. First absorption layer patterns are disposed on the reflection layer in the pattern transfer region, and a second absorption layer pattern is disposed on the reflection layer in the light blocking region. Sidewalls of the trench have a sloped profile. Related methods are also provided. | 08-01-2013 |
20130200453 | SEMICONDUCTOR DEVICES INCLUDING BIPOLAR TRANSISTORS, CMOS TRANSISTORS AND DMOS TRANSISTORS, AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices having a bipolar transistor, a CMOS transistor, a drain extension MOS transistor and a double diffused MOS transistor are provided. The semiconductor device includes a semiconductor substrate including a logic region in which a logic device is formed and a high voltage region in which a high power device is formed, trenches in the semiconductor substrate, isolation layers in respective ones of the trenches, and at least one field insulation layer disposed at a surface of the semiconductor substrate in the high voltage region. Related methods are also provided. | 08-08-2013 |
Patent application number | Description | Published |
20130119461 | SEMICONDUCTOR DEVICE HAVING A BURIED GATE AND METHOD FOR FORMING THEREOF - A semiconductor device includes: a first interlayer insulating layer in first and second regions of a semiconductor substrate, a second interlayer insulating layer over the first interlayer insulating layer in first and second regions, a hard mask provided between the first and the second interlayer insulating layers in the second region and not extending to the first region, a first metal contact formed through the second interlayer insulating layer and the hard mask in the second region, and a first storage node contact formed through the first interlayer insulating layer in the first region. | 05-16-2013 |
20130119463 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate. | 05-16-2013 |
20130130455 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased. | 05-23-2013 |
20130130458 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a gate pattern on a semiconductor substrate, performing a C ion implantation process for suppressing diffusion of dopants in the semiconductor substrate, and performing a halo ion implantation process including P ions. Therefore, a hot carrier effect due to change of a dopant profile and degradation caused by GIDL can be improved. | 05-23-2013 |
20130146968 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step. | 06-13-2013 |
20130147009 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern | 06-13-2013 |
20130162340 | MULTI-CHIP PACKAGE - A multi-chip package includes a single lead and a plurality of inner package chips. Each of the plurality of inner package chips includes at least one pad circuit and an internal circuit. The pad circuit is selectively coupled to the lead and configured to provide a chip address signal corresponding to a connection state to the lead. The inner package chip receives the chip address signal to identify a corresponding inner package chip. | 06-27-2013 |
20130168758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates. | 07-04-2013 |
20130194870 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory block including memory strings coupled to and disposed between bit lines and a common source line, and a peripheral circuit configured to perform a read operation of memory cells included in selected memory strings of the memory strings and increase channel potential of unselected memory strings in the read operation. | 08-01-2013 |
20130205074 | DATA I/O CONTROLLER AND SYSTEM INCLUDING THE SAME - A controller controls data input/output for a semiconductor memory device. The controller includes a first buffer configured to perform data transmission between an interface and the semiconductor memory device, a first control unit configured to control the semiconductor memory device according to an external request, and a second control unit configured to control the first buffer and the first control unit to simultaneously process a plurality of external requests according to a pipeline scheme. | 08-08-2013 |