Patent application number | Description | Published |
20110188387 | DETECTION OF ACTIVE NODES, SAFE NODE REMOVAL CONDITIONS, AND CROSS-CABLING CONDITIONS FOR MAINTENANCE OPERATIONS WITHIN A MULTI-CHASSIS ROUTING MATRIX - A system includes a first device connected to a second device The first device includes a second node connected to a first node and the second device via a link, and includes a backup second node connected to the first node and the second device via another link. The first node is configured to receive, via the link or the other link, a group of packets (i.e., “packets”), from the second device; display a first notification that the second node can be removed when the packets are received via only the other link; display a second notification indicating that the backup second node can be removed when the packets are received via only the link; and display a third notification indicating that neither the second node nor the backup second node can be removed when the packets are not received via only the link and via only the other link. | 08-04-2011 |
20120218996 | DETECTION OF ACTIVE NODES, SAFE NODE REMOVAL CONDITIONS, AND CROSS-CABLING CONDITIONS FOR MAINTENANCE OPERATIONS WITHIN A MULTI-CHASSIS ROUTING MATRIX - A system includes a first device connected to a second device The first device includes a second node connected to a first node and the second device via a link, and includes a backup second node connected to the first node and the second device via another link. The first node is configured to receive, via the link or the other link, a group of packets (i.e., “packets”), from the second device; display a first notification that the second node can be removed when the packets are received via only the other link; display a second notification indicating that the backup second node can be removed when the packets are received via only the link; and display a third notification indicating that neither the second node nor the backup second node can be removed when the packets are not received via only the link and via only the other link. | 08-30-2012 |
Patent application number | Description | Published |
20090292881 | DISTRIBUTED HOME-NODE HUB - A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches. | 11-26-2009 |
20090307434 | METHOD FOR MEMORY INTERLEAVE SUPPORT WITH A CEILING MASK - A distributed shared memory multiprocessor system that supports both fine- and coarse-grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes. | 12-10-2009 |
20100083066 | SYSTEM AND METHOD FOR AUTOMATIC COMMUNICATION LANE FAILOVER IN A SERIAL LINK - A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits. | 04-01-2010 |
20120290794 | REQUEST TO OWN CHAINING IN MULTI-SOCKETED SYSTEMS - A method including: receiving multiple local requests to access the cache line; inserting, into an address chain, multiple entries corresponding to the multiple local requests; identifying a first entry at a head of the address chain; initiating, in response to identifying the first entry and in response to the first entry corresponding to a request to own the cache line, a traversal of the address chain; setting, during the traversal of the address chain, a state element identified in a second entry; receiving a foreign request to access the cache line; inserting, in response to setting the state element, a third entry corresponding to the foreign request into the address chain after the second entry; and relinquishing, in response to inserting the third entry after the second entry in the address chain, the cache line to a foreign thread after executing the multiple local requests. | 11-15-2012 |
20130055011 | CACHE TAG ARRAY WITH HARD ERROR PROOFING - A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries. | 02-28-2013 |
20130086417 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 04-04-2013 |
20130138995 | DYNAMIC HYPERVISOR RELOCATION - A method for managing multiple nodes hosting multiple memory segments, including: identifying a failure of a first node hosting a first memory segment storing a hypervisor; identifying a second memory segment storing a shadow of the hypervisor and hosted by a second node; intercepting, after the failure, a hypervisor access request (HAR) generated by a core of a third node and comprising a physical memory address comprising multiple node identification (ID) bits identifying the first node; modifying the multiple node ID bits of the physical memory address to identify the second node; and accessing a location in the shadow of the hypervisor specified by the physical address of the HAR after the multiple node ID bits are modified. | 05-30-2013 |
20140040526 | COHERENT DATA FORWARDING WHEN LINK CONGESTION OCCURS IN A MULTI-NODE COHERENT SYSTEM - Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path. | 02-06-2014 |
20140181420 | DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY - A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories. | 06-26-2014 |
20140281237 | BROADCAST CACHE COHERENCE ON PARTIALLY-ORDERED NETWORK - A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request. | 09-18-2014 |
20150039938 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 02-05-2015 |
Patent application number | Description | Published |
20090011148 | Methods and apparatuses promoting adhesion of dielectric barrier film to copper - Adhesion between a copper metallization layer and a dielectric barrier film may be promoted by stabilizing a flow of a silicon-containing precursor in a divert line leading to the chamber exhaust. The stabilized gas flow is then introduced to the processing chamber to precisely form a silicide layer over the copper. This silicidation step creates a network of strong Cu—Si bonds that prevent delamination of the barrier layer, while not substantially altering the sheet resistance and other electrical properties of the resulting metallization structure. | 01-08-2009 |
20100145513 | METHOD FOR MONITORING THE POSITION OF A SEMICONDUCTOR PROCESSING ROBOT - A robotic positioning system that cooperates with a sensing system to correct robot motion is provided. The sensing system is decoupled from the sensors used conventionally to control the robot's motion, thereby providing repeatable detection of the robot's true position. In one embodiment, the positioning system includes a robot, a controller, a motor sensor and a decoupled sensor. The robot has at least one motor for manipulating a linkage controlling the displacement of a substrate support coupled thereto. The motor sensor is provides the controller with motor actuation information utilized to move the substrate support. The decoupled sensor provides information indicative of the true position the substrate support that may be utilized to correct the robot's motion. | 06-10-2010 |
20120204795 | METHODS TO IMPROVE THE IN-FILM DEFECTIVITY OF PECVD AMORPHOUS CARBON FILMS - An article having a protective coating for use in semiconductor applications and methods for making the same are provided. In certain embodiments, a method of coating an aluminum surface of an article utilized in a semiconductor processing chamber is provided. The method comprises providing a processing chamber; placing the article into the processing chamber; flowing a first gas comprising a carbon source into the processing chamber; flowing a second gas comprising a nitrogen source into the processing chamber; forming a plasma in the chamber; and depositing a coating material on the aluminum surface. In certain embodiments, the coating material comprises an amorphous carbon nitrogen containing layer. In certain embodiments, the article comprises a showerhead configured to deliver a gas to the processing chamber. | 08-16-2012 |
20120208373 | METHOD FOR DEPOSITING AN AMORPHOUS CARBON FILM WITH IMPROVED DENSITY AND STEP COVERAGE - A method for depositing an amorphous carbon layer on a substrate includes the steps of positioning a substrate in a chamber, introducing a hydrocarbon source into the processing chamber, introducing a heavy noble gas into the processing chamber, and generating a plasma in the processing chamber. The heavy noble gas is selected from the group consisting of argon, krypton, xenon, and combinations thereof and the molar flow rate of the noble gas is greater than the molar flow rate of the hydrocarbon source. A post-deposition termination step may be included, wherein the flow of the hydrocarbon source and the noble gas is stopped and a plasma is maintained in the chamber for a period of time to remove particles therefrom. | 08-16-2012 |