Patent application number | Description | Published |
20080253185 | Non-Volatile Memory and Method with Control Gate Compensation for Source Line Bias Errors - Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor. | 10-16-2008 |
20090103369 | Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output. | 04-23-2009 |
20100091568 | Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest and/or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code. | 04-15-2010 |
20100091573 | Nonvolatile Memory And Method With Reduced Program Verify By Ignoring Fastest And/Or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code. | 04-15-2010 |
20110019485 | Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output. | 01-27-2011 |
20110222345 | Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase. | 09-15-2011 |
20120243332 | Non-Volatile Memory and Method with Power-Saving Read and Program-Verify Operations - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase. | 09-27-2012 |
20130100740 | Compact Sense Amplifier for Non-Volatile Memory Suitable for Quick Pass Write - A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current. | 04-25-2013 |
20130100744 | Compact Sense Amplifier for Non-Volatile Memory - A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current. | 04-25-2013 |
20130250687 | SHARED-BIT-LINE BIT LINE SETUP SCHEME - Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell. | 09-26-2013 |
20140133229 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells. | 05-15-2014 |
20140133230 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning. | 05-15-2014 |