Singhal, Bangalore
Amankumar Singhal, Bangalore IN
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20120297358 | SYSTEM AND METHOD FOR MANAGEMENT OF A PROGRAM THROUGHOUT ITS LIFECYCLE IN AN ORGANIZATION - A system for facilitating management of one or more programs throughout their lifecycle in an organization is provided. The system comprises a Customer Relationship Management (CRM) module to create one or more programs, an Order Management System (OMS) module to create one or more tracks, and a program management module to create one or more projects. The system further comprises a resource allocation module for allocating resources for executing the one or more programs. The system further comprises a finance budgeting module for budgeting revenue, costs and profitability of the one or more programs. The system further comprises a program module that displays details of the one or more programs, the one or more tracks, and the one or more projects to one or more authorized users. The system further comprises a central repository to store data associated with the one or more programs. | 11-22-2012 |
Aman Kumar Singhal, Bangalore IN
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20080270205 | PROGRAM MANAGEMENT SYSTEMS AND METHOD THEREOF - A framework for managing a lifecycle of a program in an organization is provided. The framework includes a process module, a guiding module, a program lifecycle mapping module, and a matrix module. The process module provides a plurality of process guidelines for the one or more stages of the project management lifecycle. Further, the process module includes a strategic planning module, a financial management module, a risk management module, an organization change management module, a stake holder management module, a knowledge management module, a contractual compliance module, a governance module and a program setup module. The guiding module integrates a plurality of organizational attributes with the process guidelines of the process module. The program lifecycle mapping module maps the plurality of process guidelines with the one or more stages of the life cycle. The matrix module provides assignment of program management roles to one or more participants. | 10-30-2008 |
20100070325 | METHOD AND SYSTEM FOR ESTIMATING RESOURCE FACTORS FOR EXECUTING A PROJECT - The present invention provides a method, system and computer program product for estimating resource factors for a steady state execution of a project. The resource factors are associated with a second set of resources. A required effort associated with a first set of resources executing the project is received. Thereafter, a primary effort estimate is calculated. Subsequently, first pre-defined parameters and second pre-defined parameters are assigned corresponding weights. A value corresponding to each of the resource factors is then generated on the basis of the primary effort estimate, weighted first pre-defined parameters and weighted second pre-defined parameters and available time associated with the second set of resources. | 03-18-2010 |
20110314440 | METHOD AND SYSTEM FOR DETERMINING PRODUCTIVITY OF A TEAM ASSOCIATED WITH MAINTENANCE AND PRODUCTION SUPPORT OF SOFTWARE - The present invention provides a method, a system, and a computer program product for determining productivity of a team associated with maintenance and production support of software. The invention enables receiving one or more tickets associated with the software, the number of full time equivalent team-members (FTEs) in the team, and weight corresponding to each predefined parameter. Net ticket-units are determined based on the predefined ticket-unit associated with the tickets. An adjustment factor is determined based on the weight corresponding to each predefined parameter. Adjusted ticket-units are determined based on the net ticket-units and the adjustment factor. The productivity of the team for a predefined time period is generated based on the adjusted ticket-units and the number of FTEs. In a similar manner, the invention enables determining the number of FTEs based on a received productivity and the adjusted ticket-units. | 12-22-2011 |
20130036060 | FRAMEWORK FOR MANAGING PROJECTS IN AN ORGANIZATION - The embodiments of the present disclosure provide a framework for managing lifecycle of a project in an organization. The framework comprises a project management module configured to provide plurality of guidelines to execute a project in a global context, a behavior module configured to provide a plurality of skill sets required for the effective execution of the project, a focus module configured to generate efficient outcomes in the project performance and a support module configured to provide integrated project management. The framework provides multiple levels of project management certifications to address the competency needs as per various roles requirement in an organization. The disclosure also provides a method of implementing project management certifications which are mapped as per various roles requirements in an organization. | 02-07-2013 |
Amar Singhal, Bangalore IN
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20110075566 | Effective Bandwidth Path Metric and Path Computation Method for Wireless Mesh Networks with Wired Links - Enhanced mesh network performance is provided by computation of a path metric with respect to multi-hop paths between nodes in a mesh network and determination of a path through the mesh network that is optimal according to the path metric. Information is communicated in the mesh network according to the determined path. Nodes in the mesh network are enabled to communicate via one or more wireless links and/or one or more wired links. The path metric optionally includes an effective bandwidth path metric having elements (listed from highest to lowest conceptual priority) including an inverse of a sustainable data rate, a number of wireless links, and a number of wireless and wired links. The sustainable data rate is a measure of communication bandwidth that is deliverable by a path for a period of time. Accounting is made for interference between contiguous wireless links operating on the same channel. | 03-31-2011 |
20140185454 | Effective Bandwidth Path Metric and Path Computation Method for Wireless Mesh Networks with Wired Links - Enhanced mesh network performance is provided by computation of a path metric with respect to multi-hop paths between nodes in a mesh network and determination of a path through the mesh network that is optimal according to the path metric. Information is communicated in the mesh network according to the determined path. Nodes in the mesh network are enabled to communicate via one or more wireless links and/or one or more wired links. The path metric optionally includes an effective bandwidth path metric having elements (listed from highest to lowest conceptual priority) including an inverse of a sustainable data rate, a number of wireless links, and a number of wireless and wired links. The sustainable data rate is a measure of communication bandwidth that is deliverable by a path for a period of time. Accounting is made for interference between contiguous wireless links operating on the same channel. | 07-03-2014 |
Amit Singhal, Bangalore IN
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20140254725 | Parameter Estimation in VAMOUS Receivers - A desired signal and interfering signal are transmitted in the same timeslot and on the same frequency using an Adaptive Quadrature Phase Shift Keying (AQPSK) modulated carrier. When the Sub-Channel Power Imbalance Ratio (SCPIR) for the AQPSK modulated carrier is large and favors the interfering signal, the interfering signal is demodulated first to obtain demodulated soft bits. The demodulated soft bits corresponding to the interfering signal are then used to estimate receiver control parameters, such as Doppler shift, frequency offset, timing error, gain, etc. Using the demodulated soft bits corresponding to the interfering signal improves the accuracy of the receiver control parameters when the SCPIR is large, and results in better overall performance of the receiver. | 09-11-2014 |
Ankit Singhal, Bangalore IN
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20150292732 | PROCESS FOR RECOVERING POWER - The present invention provides a process for power recovery in a process for producing ethylene, comprising steam cracking a hydrocarbon feed to produce a cracked gas product; cooling the cracked gas product by indirect heat exchange with high pressure liquid water to obtain cooled cracked gas product while evaporating the high pressure liquid water to high pressure steam; expanding the high pressure steam in a first steam expansion turbine to produce power and to obtain medium pressure steam; heating at least part of the medium pressure steam to increase the temperature of the medium pressure steam by passing the medium pressure steam through a convection zone of the cracking furnace and retrieving reheated medium pressure steam from the convection zone; expanding at least part of the reheated medium pressure steam in a second steam expansion turbine to produce power and to obtain low pressure steam. | 10-15-2015 |
Arun Singhal, Bangalore IN
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20090306882 | SYSTEM, APPARATUS, OR METHOD FOR ENHANCED ROUTE DIRECTIONS - Embodiments of methods, apparatuses, devices and systems associated with generating a textual explanation of a route including POI information are disclosed. | 12-10-2009 |
Bhaskar Singhal, Bangalore IN
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20150339080 | BRIDGING STORAGE CONTROLLERS IN CLUSTERED DEPLOYMENTS - A storage controller receives data from a host. The data is provided to a storage stack on the storage controller. The storage stack can perform deduplication, compression or file layout operations on the data, which is then written to a first storage unit coupled to a first port of the storage controller. The storage controller determines whether a second port of the first storage controller is configured as a remote port. In response to determining that the second port is configured as a remote port, the data is also provided to a pass-thru stack on the first storage controller. The pass-thru stack performs protocol conversion on the data and writes the data to the second port on the storage controller. | 11-26-2015 |
20160098331 | METHODS FOR FACILITATING HIGH AVAILABILITY IN VIRTUALIZED CLOUD ENVIRONMENTS AND DEVICES THEREOF - A method, non-transitory computer readable medium and host computing device that stores, by a first virtual storage controller, a plurality of received transactions in a transaction log in an in-memory storage device. The first virtual storage controller is monitored and a determination is made when a failure of the first virtual storage controller has occurred based on the monitoring. When the failure of the first virtual storage controller is determined to have occurred, at least one storage volume previously assigned to the first virtual storage controller is remapped to be assigned to a second virtual storage controller. Additionally, the second virtual storage controller retrieves at least one of the transactions from the transaction log in the in-memory storage device and replays at least one of the transactions. | 04-07-2016 |
Harsh Singhal, Bangalore IN
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20120130771 | Chat Categorization and Agent Performance Modeling - Chat categorization uses semi-supervised clustering to provide Voice of the Customer (VOC) analytics over unstructured data via an historical understanding of topic categories discussed to derive an automated methodology of topic categorization for new data; application of semi-supervised clustering (SSC) for VOC analytics; generation of seed data for SSC; and a voting algorithm for use in the absence of domain knowledge/manual tagged data. Customer service interactions are mined and quality of these interactions is measured by “Customer's Vote” which, in turn, is determined by the customer's experience during the interaction and the quality of customer issue resolution. Key features of the interaction that drive a positive experience and resolution are automatically learned via machine learning driven algorithms based on historical data. This, in turn, is used to coach/teach the system/service representative on future interactions. | 05-24-2012 |
20130211880 | CHAT CATEGORIZATION AND AGENT PERFORMANCE MODELING - Chat categorization uses semi-supervised clustering to provide Voice of the Customer (VOC) analytics over unstructured data via an historical understanding of topic categories discussed to derive an automated methodology of topic categorization for new data; application of semi-supervised clustering (SSC) for VOC analytics; generation of seed data for SSC; and a voting algorithm for use in the absence of domain knowledge/manual tagged data. Customer service interactions are mined and quality of these interactions is measured by “Customer's Vote” which, in turn, is determined by the customer's experience during the interaction and the quality of customer issue resolution. Key features of the interaction that drive a positive experience and resolution are automatically learned via machine learning driven algorithms based on historical data. This, in turn, is used to coach/teach the system/service representative on future interactions. | 08-15-2013 |
Manoj Kumar Singhal, Bangalore IN
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20090157394 | SYSTEM AND METHOD FOR FREQUENCY DOMAIN AUDIO SPEED UP OR SLOW DOWN, WHILE MAINTAINING PITCH - Presented herein are system(s) and method(s) for frequency domain audio speed up or slow down, while maintaining pitch. An encoded audio signal is received. Frames from the encoded audio signal are retrieved. The frames of the audio signal are transformed into a frequency domain, wherein each of said frames are associated with a plurality of initial phases, and a corresponding plurality of ending phases. The initial phases of at least one of the frames are replaced with the ending phases of another frame. | 06-18-2009 |
Mayank Singhal, Bangalore IN
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20090171647 | INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY - A method and apparatus for ensuring efficient validation coverage of an architecture, such as protocol or interconnect architecture, is herein described. A coverage space of states for an architecture is generated and stored in a database. During simulation, states of the coverage space encountered are marked. From this, the states encountered and not encountered may be determined. Based on the states not encountered, a targeted test suite is developed to target at least some of the states not encountered during previous simulation. This feedback loop from simulation to refining of a test suite based on states of a coverage space not encountered during simulation may be recursively repeated until adequate validation, i.e. an adequate confidence level of validation, of the coverage space is achieved. | 07-02-2009 |
Nitin Singhal, Bangalore IN
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20160045152 | SYSTEM AND METHOD FOR AUTOMATED MONITORING OF FETAL HEAD DESCENT DURING LABOR - A method for automatically monitoring fetal head descent in a birth canal is presented. The method includes segmenting each image in one or more images into a plurality of neighborhood components, determining a cost function corresponding to each neighborhood component in the plurality of neighborhood components in each of the one or more images, identifying at least two structures of interest in each image in the one or more images based on the cost function, wherein the at least two structures of interest include a pubic ramus and a fetal head, measuring an angle of progression based on the at least two structures of interest, and determining the fetal head descent in the birth canal based on the angle of progression. | 02-18-2016 |
Rakshit Singhal, Bangalore IN
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20100153759 | POWER GATING TECHNIQUE TO REDUCE POWER IN FUNCTIONAL AND TEST MODES - A method and apparatus of a power gating technique to reduce power in functional and test modes are disclosed. In one embodiment, a method includes separating a power domain of a module to two distinctive sets of sub-power domains, powering a combinational logic with one of the two distinctive sets of power domains, and powering a sequential logic with the other of the two distinctive sets of power domains. The method may reduce an active and leakage power in a functional mode by gating power of the combinational logic and not gating power of the sequential logic. A system state may be retained in the sequential logic because the sequential logic remains powered during the functional mode without requiring a retention flop, an on-chip memory and/or an off-chip memory. A wake up time of the module may be reduced through the retention of the system state in the sequential logic. | 06-17-2010 |
Rakshit Kumar Singhal, Bangalore IN
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20090210759 | Scalable Scan-Based Test Architecture With Reduced Test Time And Test Power - A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported. | 08-20-2009 |
Sandeep Singhal, Bangalore IN
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20110231361 | CONSOLIDATED SECURITY APPLICATION DASHBOARD - A consolidated security application dashboard system is described wherein a plurality of endpoint systems include visibility agents that collect status and event attributes/metrics from a plurality of security applications and upload the information to datamarts on a backend server. The backend server aggregates and processed the security application attributes/metrics to enable configurable dashboards to present summary and detailed information to IT users about the security metrics relating to a group of endpoints. | 09-22-2011 |
Shobhit Singhal, Bangalore IN
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20140133613 | APPARATUS AND METHODS FOR CLOCK ALIGNMENT FOR HIGH SPEED INTERFACES - Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources. | 05-15-2014 |
Vipul Kumar Singhal, Bangalore IN
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20150188519 | DUAL EDGE-TRIGGERED RETENTION FLIP-FLOP - A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode. | 07-02-2015 |
20160065188 | LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT - Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit. | 03-03-2016 |
Vivek Singhal, Bangalore IN
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20120062298 | FLIP-FLOP ARCHITECTURE FOR MITIGATING HOLD CLOSURE - A circuit for mitigating hold closure. The circuit includes a flip-flop having a clock input and an output. The circuit also includes a multiplexer. The multiplexer includes a select input coupled to the clock input of the flip-flop. The multiplexer also includes a first data input coupled to the output of the flip-flop. Further, the multiplexer includes an output coupled to a second data input of the multiplexer. | 03-15-2012 |
20120154010 | SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC - A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed. | 06-21-2012 |
20140021993 | APPARATUSES AND METHODS TO SUPPRESS POWER SUPPLY NOISE HARMONICS IN INTEGRATED CIRCUITS - Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit. | 01-23-2014 |
20140197875 | CIRCUITS AND METHODS FOR SIGNAL INTERFERENCE MITIGATION - Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit. | 07-17-2014 |
20150323596 | METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA PACKING - An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency. | 11-12-2015 |