Patent application number | Description | Published |
20080286921 | METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES - The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness. | 11-20-2008 |
20090050471 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS - A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion. | 02-26-2009 |
20110084330 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 04-14-2011 |
20110129976 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 06-02-2011 |
20120241871 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 09-27-2012 |
20130001700 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 01-03-2013 |
20130005138 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 01-03-2013 |
20140117435 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 05-01-2014 |
20140193972 | Buried Hard Mask for Embedded Semiconductor Device Patterning - Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed. | 07-10-2014 |
Patent application number | Description | Published |
20120025209 | OPTICAL CONNECTION THROUGH SINGLE ASSEMBLY OVERHANG FLIP CHIP OPTICS DIE WITH MICRO STRUCTURE ALIGNMENT - A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels. | 02-02-2012 |
20120243837 | Combined Optical and Electrical Interface - A connection port provides electrical and/or optical interface capability. The combined electrical and optical interface port may include an optical communication light engine within the connection port itself. The connection port includes a connector housing, an electrical interface assembly, and an optical interface assembly incorporated together. One implementation of the optical communication light engine includes a laser diode to generate optical signals, a photo diode to receive optical signals, and an optical integrated circuit (IC) to control optical interface. | 09-27-2012 |
20140178009 | COMBINED OPTICAL AND ELECTRICAL INTERFACE - A connection port provides electrical and/or optical interface capability. The combined electrical and optical interface port may include an optical communication light engine within the connection port itself. The connection port includes a connector housing, an electrical interface assembly, and an optical interface assembly incorporated together. One implementation of the optical communication light engine includes a laser diode to generate optical signals, a photo diode to receive optical signals, and an optical integrated circuit (IC) to control optical interface. | 06-26-2014 |
20140270655 | OPTICAL CONNECTOR ASSEMBLY - Methods, apparatuses, and systems related to optical connector assemblies are described. In some embodiments, the connector assemblies may include an optical assembly, having an optical interconnect and an optical module, to be coupled with a host electrical connector. The connector assembly may further include springs, disposed on the optical interconnect or the host electrical connector, to facilitate a coupling of the optical interconnect with the optical module. Other embodiments are described and claimed. | 09-18-2014 |
Patent application number | Description | Published |
20100091655 | Method and apparatus for initiating routing messages in a communication network - Switches within a telecommunications network exchange so-called available bandwidth messages, each of which advertises how much bandwidth remains unassigned on a respective link. The network is of a type in which circuits are provisioned with various predefined numbers of time slots (equivalent to bandwidth). The sending of an available bandwidth message for a given link is triggered by a change in the number of time slots available on that link if that change results in a change in the number of circuit bandwidths that can be accommodated by that link for a newly provisioned circuit. | 04-15-2010 |
20110216654 | Scheme for randomized selection of equal cost links during restoration - The present invention relates generally to restoration of services in a network. More particularly, the invention encompasses a scheme for randomized selection of equal cost links during restoration in a communication network. The invention further includes multiple schemes for restoring services. The network could consist of optical, ATM, FR, or IP/MPLS switches and cross-connects. | 09-08-2011 |
20120147894 | METHODS AND APPARATUS TO PROVISION CLOUD COMPUTING NETWORK ELEMENTS - Methods and apparatus to provision cloud computing network elements are disclosed. A disclosed example method includes receiving a selection of a cloud networking template from a client, wherein the cloud networking template includes a data center connector type and a wide area network connector type, configuring a virtual machine on a host server based on the cloud networking template, configuring a data center connector based on the data center connector type, configuring a wide area network connector based on the wide area network connector type, and coupling the wide area network connector to the data center connector and coupling the data center connector to the virtual machine within the host server to enable the client to access the virtual machine. | 06-14-2012 |
20140223434 | Methods and Apparatus to Provision Cloud Computing Network Elements - Methods and apparatus to provision cloud computing network elements are disclosed. A disclosed example method includes receiving a selection of a cloud networking template from a client, wherein the cloud networking template includes a data center connector type and a wide area network connector type, configuring a virtual machine on a host server based on the cloud networking template, configuring a data center connector based on the data center connector type, configuring a wide area network connector based on the wide area network connector type, and coupling the wide area network connector to the data center connector and coupling the data center connector to the virtual machine within the host server to enable the client to access the virtual machine. | 08-07-2014 |