Patent application number | Description | Published |
20080303021 | Optimized Thermally Conductive Plate and Attachment Method for Enhanced Thermal Performance and Reliability of Flip Chip Organic Packages - Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature. | 12-11-2008 |
20090095444 | MICROJET MODULE ASSEMBLY - Low-pressure drop thermal assemblies, systems and methods of making low-pressure drop thermal assemblies for use in high power flux situations. A manifold body is attached to a distributor to form a subassembly. This subassembly is in communication with a substrate surface, which has a semiconductor device in need of thermal management thereon. An enclosed cavity is formed between the target substrate surface and the subassembly, and a seal of the cavity protects critical components residing on the active surface of the semiconductor device. The distributor includes a distributed liquid impingement microjet inlet array isolated from and parallel with a distributed microjet drain array for impinging cooling fluid and removing spent heated fluid in a direction orthogonal to a target surface for maximizing the heat transfer rate, and thereby providing high cooling flux capabilities while enabling low-pressure drops. | 04-16-2009 |
20090098666 | CHIP PACKAGE ASSEMBLY USING CHIP HEAT TO CURE AND VERIFY - Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used. | 04-16-2009 |
20090174084 | VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING - The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip. | 07-09-2009 |
20100019377 | SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT - An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM. | 01-28-2010 |
20100020503 | LID EDGE CAPPING LOAD - A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive. After the thermal interface material has and adhesive have cured, the method removes the force from near the distal ends of the lid or substrate to cause the center portion of the lid to return to a position closer to the semiconductor chip, creating a residual compressive stress in the thermal interface material thus improving thermal performance and thermal reliability. | 01-28-2010 |
20100327430 | SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER - Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE | 12-30-2010 |
20120080784 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 04-05-2012 |
20120196408 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 08-02-2012 |
20120326294 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The method comprises adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting comprises placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further comprise lowering the lid until the pistons contact the chip shim. The method further comprises separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further comprises dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further comprises sealing the lid to the chip carrier with sealant. | 12-27-2012 |
20130027063 | DETERMINING THERMAL INTERFACE MATERIAL (TIM) THICKNESS CHANGE - An apparatus for determining a thickness change of thermal interface material (TIM) disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the TIM thickness is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to the TIM thickness change. | 01-31-2013 |
20140024465 | ELECTRONIC DEVICE CONSOLE WITH NATURAL DRAFT COOLING - An electronic device console includes a console body that houses a chip package, and a duct extending from the console body. An interior volume of the duct is in fluid communication with an interior volume of the console body. A first vent is at a distal end of the duct. A second vent is in a wall of the console body. The console may be oriented in a first orientation and a second orientation. The duct functions as a chimney for natural convection cooling of the chip package when the console is oriented in the first orientation. The console body functions as a chimney for natural convection cooling of the chip package when the console is oriented in the second orientation. | 01-23-2014 |
20140027898 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The method includes adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting includes placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further includes lowering the lid until the pistons contact the chip shim. The method further includes separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further includes dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further includes sealing the lid to the chip carrier with sealant. | 01-30-2014 |
20140051211 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 02-20-2014 |
20140284040 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 09-25-2014 |
20140331792 | DETERMINING MAGNITUDE OF COMPRESSIVE LOADING - An apparatus for determining a magnitude of a compressive load applied to a piston including a compliant film disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the magnitude of the compressive load is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to a deformation of the compliant film as the compressive load is applied. | 11-13-2014 |
20150077944 | MULTICHIP MODULE WITH STIFFENING FRAME AND ASSOCIATED COVERS - A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings. | 03-19-2015 |
Patent application number | Description | Published |
20110180923 | RELIABILITY ENHANCEMENT OF METAL THERMAL INTERFACE - A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated. | 07-28-2011 |
20120007229 | ENHANCED THERMAL MANAGEMENT OF 3-D STACKED DIE PACKAGING - A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate. | 01-12-2012 |
20120039046 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The method includes contacting pistons of a lid with respective ones of chips on a chip carrier. The method further includes separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier. The at least one seal shim has a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier. The method further includes dispensing thermal interface material within the gap and in contact with the chips. The method further includes sealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier. | 02-16-2012 |
20120241944 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The structure includes a lid encapsulating at least one chip mounted on a chip carrier; at least one seal shim fixed between the lid and the chip carrier, the at least one seal shim forming a gap between pistons of the lid and respective ones of the chips; and thermal interface material within the gap and contacting the pistons of the lid and respective ones of the chips. | 09-27-2012 |