Patent application number | Description | Published |
20090157946 | MEMORY HAVING IMPROVED READ CAPABILITY - In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency. | 06-18-2009 |
20090219760 | MEMORY DEVICE HAVING READ CACHE - A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories. | 09-03-2009 |
20100088459 | Improved Hybrid Drive - A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time. | 04-08-2010 |
20100125444 | Method And Apparatus For Reducing Read Latency In A Pseudo Nor Device - A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus. The memory controller has a NOR memory for storing program code for initiating the operation of the memory controller, and for receiving NOR commands from the first bus and issuing NAND protocol commands on the second bus, in response thereto, to emulate the operation of a NOR memory device. The program code causes the memory controller to read a first sector of bits from the page buffer of the NAND memory and to write the sector of bits into the RAM memory, wherein the first sector contains the location of the desired address, and supplying data from said RAM memory in response to the read operation. | 05-20-2010 |
20100312926 | SWITCH FOR A TWO WAY CONNECTION BETWEEN A REMOVABLE CARD, A MOBILE WIRELESS COMMUNICATION DEVICE, OR A COMPUTER - A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch. | 12-09-2010 |
20110252185 | Method Of Operating A NAND Memory Controller To Minimize Read Latency Time - A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host. | 10-13-2011 |
20110296080 | Method Of Writing To A NAND Memory Block Based File System With Log Based Buffering - A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation. | 12-01-2011 |
20110296276 | Dynamic Buffer Management In A NAND Memory Controller To Minimize Age Related Performance Degradation Due To Error Correction - An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port. A bus connects to each of the storage circuits and to each other and supplies data bits between each storage circuit and between the nonvolatile memory and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the plurality of data bits; or the plurality of corrected data bits, and supplies same to the input/output port of the associated storage circuit and stores same as storage bits in the storage circuit, and supplies the storage bits as output of the storage circuit. | 12-01-2011 |
20120117305 | Method Of Storing Blocks Of Data In A Plurality Of Memory Devices For High Speed Sequential Read, A Memory Controller And A Memory System - A method for controlling the storage of a plurality of blocks of sequential data in a plurality of independent NAND memory devices, where each NAND memory device can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The method includes assigning a different NAND memory device to each different block of data received for storage and for storing the plurality of blocks of data in the plurality of different NAND memory devices. Efficiency of readout of sequential blocks of data is improved. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method. | 05-10-2012 |
20120117444 | Method Of Storing Blocks Of Data In A Plurality Of Memory Devices In A Redundant Manner, A Memory Controller And A Memory System - A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method. | 05-10-2012 |
20130124778 | METHOD OF STORING HOST DATA AND META DATA IN A NAND MEMORY, A MEMORY CONTROLLER AND A MEMORY SYSTEM - A host device connected to memory devices, with each memory device having NAND memory chips and an associated controller. Each NAND memory chip can store a page of data in a single write operation, and can read a page of data from NAND memory in a single read operation, with the page being the smallest unit of storage and having a plurality of bits. The controller of each memory chip partitions each page of the associated NAND memory chip into first, second and third locations. The first location is for storage of host data. The second location is for storage of controller meta data. The third location is for storage of meta data of the host device associated with the host data. The host data, meta data of the controller, and meta data of the host device are written into or read from a page in a single operation. | 05-16-2013 |
20150039813 | NAND Interface Capacity Extender Device For Extending Solid State Drives Capacity, Performance, And Reliability - A system and method for a solid state drive comprising a system controller and one or more extender devices coupled to the system controller is disclosed, where each extender device is coupled to a plurality of NAND storage devices and each NAND storage device comprising a plurality of NAND flash memory cells. | 02-05-2015 |