Patent application number | Description | Published |
20080206942 | METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS - A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants. | 08-28-2008 |
20100148271 | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device - The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift. | 06-17-2010 |
20120080721 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor structure includes a recess disposed in a substrate, a non-doped epitaxial layer and a doped epitaxial layer. The non-doped epitaxial layer is disposed on the inner surface of the recess and substantially consists of Si and an epitaxial layer. The non-doped epitaxial layer has a sidewall and a bottom which together cover the inner surface. The bottom thickness is not greater than 120% of the sidewall thickness. The non-doped epitaxial layer and the doped epitaxial layer together fill up the recess. | 04-05-2012 |
20120248511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-04-2012 |
20120270377 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE - A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process. | 10-25-2012 |
20120292638 | PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE - A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface. | 11-22-2012 |
20120299157 | SEMICONDUCTOR PROCESS AND FABRICATED STRUCTURE THEREOF - A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process. | 11-29-2012 |
20120326238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure. | 12-27-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130020657 | METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. | 01-24-2013 |
20130026543 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle. | 01-31-2013 |
20130092954 | Strained Silicon Channel Semiconductor Structure and Method of Making the Same - A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased. | 04-18-2013 |
20130122691 | METHOD FOR MAKING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess. | 05-16-2013 |
20130256701 | STRAINED SILICON CHANNEL SEMICONDUCTOR STRUCTURE - A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses. | 10-03-2013 |
20130264585 | SEMICONDUCTOR DEVICE WITH STRESS-PROVIDING STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface. | 10-10-2013 |
20130288446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-31-2013 |
20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 02-06-2014 |