Patents - stay tuned to the technology

Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Shu-Ming Chang

Shu-Ming Chang, Tucheng City TW

Patent application numberDescriptionPublished
20080305624Bonding Structure With Buffer Layer And Method Of Forming The Same - A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.12-11-2008
20100230803ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.09-16-2010
20100289092POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.11-18-2010
20110042819CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.02-24-2011
20110084382CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.04-14-2011
20110127670CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.06-02-2011
20110233782ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.09-29-2011
20120241923IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME - An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.09-27-2012
20140154840CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.06-05-2014

Patent applications by Shu-Ming Chang, Tucheng City TW

Shu-Ming Chang, Taipei TW

Patent application numberDescriptionPublished
20110042796CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.02-24-2011
20110140267ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.06-16-2011

Shu-Ming Chang, Yangmei Town TW

Patent application numberDescriptionPublished
20110007062DISPLAY PANEL AND DRIVING METHOD THEREOF - A display panel and a driving method thereof are disclosed. The display panel comprises a plurality of pixel rows, a plurality of data lines and a plurality of gate lines. Each of the pixel rows includes pairs of first and second pixels adjacent to each other. The data lines are positioned between the first and the second pixels, respectively. The gate lines include first, second, third and fourth gate lines arranged in an alternating manner. The method comprises the following steps: turning on the gate lines in a sequence of first, second, fourth and third gate lines; and transmitting the data signal to the pixels through the data lines. The panel is applicable to an LCD panel and an LCD apparatus.01-13-2011

Shu-Ming Chang, Nantou TW

Patent application numberDescriptionPublished
20100286610Disposable safety syringe with retractable needle - A disposable safety syringe in one embodiment includes a stepped syringe barrel comprising two opposite mating members on an inner surface proximate a distal end; a plunger comprising a connection member and a breakable section behind the connection member; a first needle assembly comprising a needle and a needle hub secured to the distal end of the syringe barrel; and a hollow second needle assembly shaped to lockingly secure to the first needle assembly in the syringe barrel, the second needle assembly comprising two opposite corresponding mating members on an outer surface, the corresponding mating members being lockingly engaged with the mating members. After dispensing, the plunger may clockwise rotate about the syringe barrel until the mating members and the corresponding mating members are unlocked lengthwise each other. The plunger, the second needle assembly, and the first needle assembly may move rearward to retract the needle within the syringe barrel.11-11-2010

Shu-Ming Chang, Taipei County TW

Patent application numberDescriptionPublished
20090283872PACKAGE STRUCTURE OF THREE-DIMENSIONAL STACKING DICE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a package structure of three-dimensional stacking dice and its manufacturing method. This invention employs the Through-Silicon-Vias (TSVs) technology to establish vertical electrical connection of the three-dimensional stacking dice and a redistribution layer between a blind hole-on-pad and a vertical through hole formed by the TSVs technology to direct the electrical connection from a first surface to an opposite second surface of this structure. In addition, this invention employs a conductive bump completely covering the pads jointed together between the stacking dice to avoid breakage of the pads. The reliability of the three-dimensional stacking dice of the present invention is increased.11-19-2009
20100020502Wafer-To-Wafer Stacking - a wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.01-28-2010
20100032830THREE-DIMENSIONAL CONDUCTING STRUCTURE AND METHOD OF FABRICATING THE SAME - The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.02-11-2010
20100052099CAPACITOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.03-04-2010
20100163090THERMOELECTRIC DEVICE AND FABRICATION METHOD THEREOF, CHIP STACK STRUCTURE, AND CHIP PACKAGE STRUCTURE - A thermoelectric device including a first substrate, a plurality of conductive vias, a second substrate, a thermoelectric couple module, a first insulation layer, and a second insulation layer is provided. The first substrate has a first surface and a second surface opposite to each other. The conductive vias running through the first substrate respectively connect the first and the second surface. The second substrate faces the second surface of the first substrate. The thermoelectric couple module including a plurality of thermoelectric couples connected with each other in series is disposed between the first and the second substrate and coupled to the conductive vias. The first insulation layer is disposed between the thermoelectric couple module and the first substrate. The second insulation layer is disposed between the thermoelectric couple module and the second substrate.07-01-2010

Shu-Ming Chang, Sinjhuang City TW

Patent application numberDescriptionPublished
20090267536Fluorescent lamp driver circuit - A fluorescent lamp driver circuit is provided. The fluorescent lamp driver circuit uses reversed current detecting signal to achieve feedback control and circuit protection so as to simplify the driver circuit and reduces the number of the required electronic components. The driver circuit needs a single control unit to control the whole circuit, which not only reduces cost, but also simplifies circuit design.10-29-2009

Shu-Ming Chang, Tainan County TW

Patent application numberDescriptionPublished
20080265791BACKLIGHT MODULE AND CURRENT PROVIDING CIRCUIT THEREOF - A backlight module and a current providing circuit thereof are provided. The current providing circuit includes a signal generating unit, a switching unit, a first capacitor, a transformer and an output node. The signal generating unit generates a PWM signal according to a level of a power source. The switching unit determines whether a first signal end and a second signal end of the switching unit are conducted according to the PWM signal received by a control end of the switching unit. Following a switch performed by the switching unit, the first capacitor charges and discharges through a current path provided by a primary coil of the transformer. Thereby, a secondary coil of the transformer generates a corresponding AC voltage by sensing a current change in the primary coil and outputs the AC voltage through the output node.10-30-2008
20080297499LCD POWER SUPPLY - An LCD (liquid crystal display) power supply includes an AC to DC converter circuit, a transformer, a DC to AC converter, and a feedback circuit. The AC to DC converter circuit couples an AC power supply to generate a DC signal. The DC to AC converter couples the DC signal to a primary side of the transformer and alternates polarities thereof so that an AC signal is generated on a secondary side of the transformer to supply for a load. The feedback circuit receives a first feedback signal indicative of power being supplied to the load and modulates the DC signal generated by the AC to DC converter circuit according to the first feedback signal.12-04-2008
20090108771DRIVING SYSTEM FOR ELECTRONIC DEVICE AND CURRENT BALANCING CIRCUIT THEREOF - A driving system, includes: a power supply unit for providing a first current and a second current; a first transformer having a primary side coupled to the power supply unit and a secondary side coupled to a first current balancing circuit for driving a plurality of first lamps; a second transformer having a primary side coupled to the power supply unit and a secondary side coupled to a second current balancing circuit for driving a plurality of second lamps; a balancing control circuit coupled to the power supply unit for balancing the first and the second current so that the first current and the second current are substantially equal.04-30-2009
20090237346INVERTER CIRCUIT OF DRIVING A LAMP AND BACKLIGHT MODULE USING THE SAME - An inverter circuit for driving a lamp and a backlight module using the same are provided. The inverter circuit includes a signal generation module, a switching unit, a first capacitor, a transformer and a first detecting module. The signal generation module generates a pulse width modulation (PWM) signal, wherein the duty cycle of the PWM signal is controlled by a feedback signal and a sensed signal. The switching unit has a control terminal receiving the PWM signal, and has a first current terminal and a second current terminal respectively coupled to a first terminal and a second terminal of the first capacitor. The transformer generates an AC driving signal to the lamp according to a signal variation of the primary winding coupled the first current terminal of the first transistor. The first detecting module generates the sensed signal according to the flowing current of the switching unit.09-24-2009
20090244946DC-AC CONVERTER - A DC-AC converter includes a signal generating module, a first switch, a first capacitor, a transformer, and a trigger signal generating module. The signal generating module generates a pulse width modulation (PWM) signal according to a trigger signal. The first switch has a control terminal receiving the PWM signal, and a first terminal and a second terminal coupled to a first terminal and a second terminal of the first capacitor respectively. The transformer has a primary winding coupled to the second terminal of the first switch, and a secondary winding coupled to a load. The transformer generates a driving signal to the load according to a signal variation of the primary winding. The trigger signal generating module compares a first signal outputted from the second terminal of the first switch with a phase delay signal thereof and thereby generates the trigger signal for controlling the frequency of the PWM signal.10-01-2009

Shu-Ming Chang, Tainan TW

Patent application numberDescriptionPublished
20090189536HIGH EFFICIENCY AND LOW COST COLD CATHODE FLUORESCENT LAMP DRIVING APPARATUS FOR LCD BACKLIGHT - The invention is a driving apparatus and circuit for efficiently converting a direct current (DC) signal into an alternating current (AC) signal to drive a fluorescent lamp. A semi class E configuration which utilizes only one transistor is employed in the invention. The invention comprises a power transistor, a transformer wherein a primary winding is used as a load for the power transistor and a secondary winding is used to transfer energy to the load for the driving apparatus, i.e. the CCFL tube, and control means which extracts the frequency and current of the power transistor and corrects the deviation between the frequency of the power transistor and that of the control means.07-30-2009

Shu-Ming Chang, Hsinchu TW

Patent application numberDescriptionPublished
20080265410Wafer level package - A wafer level package includes a substrate, a passivation layer, an elastic layer, a first insulation layer, a metal trace, a second insulation layer, and a bump. The passivation layer is formed on the substrate, and has one pad. The elastic layer is formed on the passivation layer. The first insulation layer is formed on the passivation layer and the elastic layer, and has a junction in contact with the pad. The metal trace is formed on the first insulation layer. The second insulation layer is formed on the metal trace, and a groove is formed correspondingly above the elastic layer. The bump is formed in the groove. An annular trench can be further formed around the bump. A groove can be furthermore formed in the first insulation layer correspondingly below the bump.10-30-2008
20080308928Image sensor module with a three-dimensional die-stacking structure - This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.12-18-2008
20090045488Magnetic shielding package structure of a magnetic memory device - This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.02-19-2009
20090134527STRUCTURE OF THREE-DIMENSIONAL STACKED DICE WITH VERTICAL ELECTRICAL SELF-INTERCONNECTIONS AND METHOD FOR MANUFACTURING THE SAME - This invention provides a structure of three-dimensional stacked dice with vertical electrical self-interconnections and a method for manufacturing the same. A respective electrical conductive layer is formed in a buried layer of each of the stacked dice, and being extended and exposed to a sidewall of the respective die. An electroless plating process is performed to deposit metal on exposed portions of the respective electrical conductive layers. The metal isotropically grows along the sidewalls of the stacked dice to form a vertical electrical conductive wire connecting the respective conductive layers. The vertical electrical self-interconnections of the three dimensional stacked dice are established.05-28-2009

Patent applications by Shu-Ming Chang, Hsinchu TW

Shu-Ming Chang, Hsin Chu Hsien TW

Patent application numberDescriptionPublished
20090014891Three-dimensional die-stacking package structure and method for manufacturing the same - This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.01-15-2009

Shu-Ming Chang, New Taipei City TW

Patent application numberDescriptionPublished
20110193225ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.08-11-2011
20110227186IMAGE SENSOR PACKAGE AND FABRICATION METHOD THEREOF - An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.09-22-2011
20110291228PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.12-01-2011
20120146108CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.06-14-2012
20120146111CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention provides a chip package including a semiconductor substrate, a drain electrode, a source electrode and a gate electrode. The semiconductor substrate has a first surface and an opposite second surface wherein the second surface has a recess. The drain electrode is disposed on the first surface and covers the recess. The source electrode is disposed on the second surface in a position corresponding to the drain electrode covering the recess. The gate electrode is disposed on the second surface. An embodiment of the invention further provides a manufacturing method of a chip package.06-14-2012
20120146153CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.06-14-2012
20120168939CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.07-05-2012
20120267780CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.10-25-2012
20120313222CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.12-13-2012
20120313261CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.12-13-2012
20130045571METHOD FOR FABRICATING ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.02-21-2013
20130062759ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.03-14-2013
20130126086ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.05-23-2013
20130127022ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.05-23-2013
20130193520POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.08-01-2013
20130207240CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.08-15-2013
20130292825CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.11-07-2013
20130307161CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.11-21-2013
20130320559CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.12-05-2013
20140091441IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME - An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.04-03-2014
20140193950ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.07-10-2014
20140203387SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THEREOF - Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.07-24-2014
20140252659SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.09-11-2014
20140264771CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.09-18-2014
20140264785CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.09-18-2014
20140284792ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.09-25-2014
20140306343CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.10-16-2014
20140332908CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.11-13-2014
20140332968CHIP PACKAGE - A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.11-13-2014
20140332969CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.11-13-2014
20140332983STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.11-13-2014

Patent applications by Shu-Ming Chang, New Taipei City TW

Shu-Ming Chang US

Patent application numberDescriptionPublished
20120226241SAFETY SYRINGE WITH RETRACTABLE ROTATION - A safety syringe with retractile rotation is disclosed. The plunger is capable of rapidly embedding with and positioning at the needle set, the next step of the retractile movement to retract the needle is easily processed by a user, and the needle set is firmly assembled and positioned at the open end of the barrel so as to not easily result an unpredictable phenomenon, such as deteriorating the suitability between the needle set and the barrel to result the needle set indentation and leakage when injecting from a sharp raise in temperatures, or overtightening the needle set and the barrel to result the needle and the needle set incapable of retracting in the barrel from the sharp fall of temperature. Furthermore, this invention is capable of achieving one hand operation with safety, improving environmental protection quantity, and easy use for retracting the needle.09-06-2012

Shu-Ming Chang, Tucheng Dist TW

Patent application numberDescriptionPublished
20140073089CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.03-13-2014

Shu-Ming Chang, Jhongli City TW

Patent application numberDescriptionPublished
20130168784SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.07-04-2013

Shu-Ming Chang, Taoyuan County TW

Patent application numberDescriptionPublished
20140158513TOUCH PANEL - A touch panel connected with p signal channels of a chip is provided. The touch panel includes a substrate, electrode pairs, and signal lines. The electrode pairs are arranged in a matrix of q columns and r rows and each includes a first electrode connected to the h06-12-2014
Website © 2015 Advameg, Inc.