Patent application number | Description | Published |
20120063990 | METHOD FOR FORMING GRANULAR POLYNARY NANO COMPOUND - The invention discloses a method for forming granular polynary nano compound, which comprises the steps of (S | 03-15-2012 |
20130181605 | DISPLAY PANEL - A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly. | 07-18-2013 |
20130327561 | BONDING STRUCTURE - A bonding structure includes a substrate, multiple first pads, multiple second pads, an insulation layer and a patterned conductive layer. The substrate has a bonding region and a predetermined-to-be-cut region. The first pads are disposed on the substrate and within the bonding region. The second pads are disposed on the substrate and within the predetermined-to-be-cut region. The insulation layer is disposed on the substrate and covers the first and second pads. The insulation layer has multiple first and second openings respectively exposing parts of the first and second pads. The patterned conductive layer is disposed on the substrate and covers the insulation layer and the parts of the first and second pads exposed out by the first and second openings, in which the patterned conductive layer is electrically connected to the first and second pads via the first and second openings. | 12-12-2013 |
20140192402 | ELECTROPHORETIC DISPLAY APPARATUS - An electrophoretic display apparatus is suitable for being electrically connected to an external circuit and includes a drive array substrate, an electrophoretic display film and a first optical adhesive layer. The electrophoretic display film is disposed on the drive array substrate and includes a flexible substrate and a display medium layer. The flexible substrate has a disposed region and a bonding region. The external circuit is disposed between the flexible substrate and the drive array substrate, located in the bonding region and extends outside the drive array substrate. The display medium layer is disposed between the flexible substrate and the drive array substrate and located in the disposed region. The first optical adhesive layer is disposed between the display medium layer and the drive array substrate. A thickness of the external circuit is substantially a sum of that of the display medium layer and the first optical adhesive layer. | 07-10-2014 |
20140361301 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes. | 12-11-2014 |
20150206470 | PIXEL ARRAY - A pixel array including first and second signal lines, an active device, a pixel electrode and selection lines is provided. The second signal lines are intersected with the first signal lines to drive the active device, and the pixel electrode is connected to the active device. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines, where at least one selective line is disposed between the adjacent two second signal lines. An amount ratio of the first signal lines and the selection lines is a | 07-23-2015 |
20160042683 | DISPLAY PANEL - A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes. | 02-11-2016 |
20160099260 | DISPLAY PANEL - A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transmitting lines, and a driving chip. The transmitting lines are disposed on the substrate and electrically connected to the second signal lines. The driving chip includes a plurality of first pins, a plurality of second pins, and a driving circuit. The first pins are electrically connected to the first signal lines, and the second pins are electrically connected to the transmitting lines. The first pins and the second pins are disposed alternately and evenly, such that the first signal lines and the transmitting lines do not intersect each other. The transmitting lines are disposed on the substrate evenly. | 04-07-2016 |
Patent application number | Description | Published |
20120219897 | PHOTORESIST HAVING IMPROVED EXTREME-ULTRAVIOLET LITHOGRAPHY IMAGING PERFORMANCE - Provided is a photoresist that includes a polymer is free of a aromatic group and a photo acid generator (PAG) that has less than three aromatic groups. In an embodiment, the PAG includes an anion component and a cation component. The anion component has one of the following chemical formulas: | 08-30-2012 |
20140038086 | Phase Shift Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same - A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an Ag | 02-06-2014 |
20140111781 | METHOD AND APPARATUS FOR ULTRAVIOLET (UV) PATTERNING WITH REDUCED OUTGASSING - A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus. | 04-24-2014 |
20140256146 | Method and Structure to Improve Process Window for Lithography - The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process | 09-11-2014 |
20140347644 | SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION - Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height. | 11-27-2014 |
20150085264 | ROTARY EUV COLLECTOR - An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force. | 03-26-2015 |
20150241776 | Method for Lithography Patterning - A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing. | 08-27-2015 |
20150262836 | Method for Integrated Circuit Patterning - Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern. | 09-17-2015 |
20150286138 | Photoresist Having Improved Extreme-Ultraviolet Lithography Imaging Performance - Provided herein is a photoresist compound with improved extreme-ultraviolet lithography image performance. The photoresist includes a polymer that is free of an aromatic group and a photo acid generator (PAG) free of aromatic groups. The PAG includes an anion component and a cation component, wherein the anion component has one of the several specified chemical formulas and the cation component also has a specified chemical formula. The anion component includes a material selected from the group consisting of methyl and ethyl and the cation component includes a material selected from the group consisting of: an alkyl group, an alkenyl group, and an oxoalkyl group. | 10-08-2015 |
20150323862 | PARTICLE REMOVAL SYSTEM AND METHOD THEREOF - A method of removing particles from a surface of a reticle is disclosed. The reticle is placed in a carrier, a source gas is flowed into the carrier, and a plasma is generated within the carrier. Particles are then removed from a surface of the reticle using the generated plasma. A system of removing particles from a surface includes a carrier configured to house a reticle, a reticle stocker including the carrier, a power supply configured to apply a potential between an inner cover and an inner baseplate of the carrier, and a gas source configured to flow a gas into the carrier. A plasma may be generated within the carrier, and particles can be removed from a surface of the reticle using the generated plasma. An acoustic energy source configured to agitate at least one of the source gas and the generated plasma may be provided to facilitate particle removal using an agitated plasma. | 11-12-2015 |
20150332922 | Semiconductor Integrated Circuit Fabrication With Pattern-Reversing Process - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer. | 11-19-2015 |
20160054664 | SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION - Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height. | 02-25-2016 |
Patent application number | Description | Published |
20140098433 | WAFER LEVEL LENS, LENS SHEET AND MANUFACTURING METHOD THEREOF - A method of manufacturing a lens sheet including following steps is provided. A first structure is provided. The first structure includes a first transparent substrate and a first lens film attached to the first transparent substrate. A second structure is provided. The second structure includes a second transparent substrate and a second lens film. The second transparent substrate has a first surface and a second surface opposite to the first surface. The second lens film is attached to the first surface. The first lens film is attached to the second lens film. A third lens film is formed on the second surface of the second substrate after the first lens film is attached to the second lens film. Moreover, a lens sheet and a wafer level lens are also provided. | 04-10-2014 |
20140204467 | WAFER LEVEL OPTICAL LENS STRUCTURE - A wafer level optical lens structure is provided. A stress buffer layer is disposed between a light-transmissive substrate and a lens layer, so as to improve production yield of the wafer level optical lens. | 07-24-2014 |
20150062714 | IMAGE-CAPTURING ASSEMBLY AND ARRAY LENS UNITS THEREOF - A lens module is disclosed. The lens module includes a substrate assembly and an array of lens units. The substrate assembly includes a main body and a supporting layer formed on the substrate assembly. The main body has a front surface, a rear surface opposite to the front surface, and at least one lateral surface connecting the front surface to the rear surface. The supporting layer has a planar configuration and is formed on the main body. The main body is made of a first material and the supporting layer is made of a second material different from the first material. | 03-05-2015 |
20150331155 | WAFER LEVEL LENS, LENS SHEET - A lens sheet including a first transparent substrate, a first lens film, a second lens film, a second transparent substrate, a plurality of bonding material patterns and a plurality of buffer cavities is provided. The first lens film is disposed on the first transparent substrate, and having a plurality of first lens portions and a plurality of first carrying portions. The second lens film is disposed between the second transparent substrate and the first lens film. The bonding material patterns are disposed between the second lens film and the first carrying portions. The buffer cavities are located between the first carrying portions and the first lens portions. | 11-19-2015 |