Patent application number | Description | Published |
20110018093 | PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER - In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein. | 01-27-2011 |
20110101538 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 05-05-2011 |
20110108992 | AIR GAP INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines. | 05-12-2011 |
20110272812 | STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS - Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level. | 11-10-2011 |
20120012980 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. | 01-19-2012 |
20120153503 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 06-21-2012 |
20120171859 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 07-05-2012 |
20120248508 | FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS - Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer. | 10-04-2012 |
20120326237 | LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks. | 12-27-2012 |
20130065376 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. | 03-14-2013 |
20130112462 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer. | 05-09-2013 |
20130134513 | FINFET WITH IMPROVED GATE PLANARITY - A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged. | 05-30-2013 |
20130285208 | FINFET DIODE WITH INCREASED JUNCTION AREA - A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer. | 10-31-2013 |
20140070357 | SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS - A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned. | 03-13-2014 |
Patent application number | Description | Published |
20130130489 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A method for forming a sealed air gap for a semiconductor chip including forming a gate over a substrate; forming a sacrificial spacer adjacent to the gate; forming a first dielectric layer about the gate and the sacrificial spacer; forming a contact to the gate; substantially removing the sacrificial spacer, wherein a space is formed between the gate and the first dielectric layer; and forming a sealed air gap in the space by depositing a second dielectric layer over the first dielectric layer. | 05-23-2013 |
20130320546 | DUAL-METAL SELF-ALIGNED WIRES AND VIAS - Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. | 12-05-2013 |
20140054699 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140068541 | INTERCONNECT STRUCTURES AND METHODS FOR BACK END OF THE LINE INTEGRATION - A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. | 03-06-2014 |
20140070282 | SELF-ALIGNED CONTACTS - Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure. | 03-13-2014 |
20140099769 | METHOD TO PROTECT AGAINST CONTACT RELATED SHORTS ON UTBB - Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches. | 04-10-2014 |
20140110794 | FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION - Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process. | 04-24-2014 |
20140191296 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 07-10-2014 |
20140191323 | METHOD OF FORMING FINFET OF VARIABLE CHANNEL WIDTH - Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs. | 07-10-2014 |
20140217592 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 08-07-2014 |
20140231885 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers. | 08-21-2014 |
20140231918 | FINFETS AND FIN ISOLATION STRUCTURES - FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures. | 08-21-2014 |
20140256106 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 09-11-2014 |
20140264496 | STRESS ENHANCED FINFET DEVICES - A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack. | 09-18-2014 |
20140264598 | STRESS ENHANCED FINFET DEVICES - A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack. | 09-18-2014 |
20140326698 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon. | 11-06-2014 |
20140339629 | CONTACT FORMATION FOR ULTRA-SCALED DEVICES - Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling. | 11-20-2014 |
20140342549 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 11-20-2014 |
20140353753 | FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY - Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET. | 12-04-2014 |
20140353767 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 12-04-2014 |
20140363941 | REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER - A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. | 12-11-2014 |
20150014772 | PATTERNING FINS AND PLANAR AREAS IN SILICON - A method including for forming a plurality of mandrels, a plurality of sidewall spacers, and a plurality of offset spacers above a hardmask layer, the sidewall spacers being separated by the plurality of mandrels and the plurality of offset spacers in an alternating order, each of the plurality of sidewall spacers being in direct contact with a single offset spacer and a single mandrel, the plurality of mandrels being separated from the plurality of offset spacers by the plurality of sidewall spacers, depositing a fill material above the plurality of mandrels, above the plurality of sidewall spacers, above the plurality of offset spacers, and above the hardmask layer, and removing the plurality of mandrels and the plurality of offset spacers selective to the plurality of sidewall spacers, the fill material, and the hardmask layer. | 01-15-2015 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150041868 | SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS - A semiconductor device is provided that includes a gate structure that is present on a channel portion of a semiconductor substrate that is present between a source region and a drain region. The gate structure includes at least a gate conductor and a gate sidewall spacer that is adjacent to the at least one gate conductor. An upper surface of the gate conductor is recessed relative to an upper surface of the gate sidewall spacer. A multi-layered cap is present on the upper surface of the gate conductor. The multi-layered cap includes a high-k dielectric material and a dielectric cap spacer that is present on a portion of the high-k dielectric material that is present on the sidewall of the gate sidewall spacer. | 02-12-2015 |
20150041905 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR TRANSISTORS AND THE RESULTING DEVICES - Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers. | 02-12-2015 |
20150054033 | FINFET WITH SELF-ALIGNED PUNCHTHROUGH STOPPER - A finFET with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finFET device. The method further includes forming a punchthrough stopper on exposed sidewalls of the fin structures, below the spacers. The method further includes diffusing dopants from the punchthrough stopper into the fin structures. The method further includes forming source and drain regions adjacent to the gate structure and fin structures. | 02-26-2015 |
20150054078 | METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SMEICONDUCTOR PRODUCTS - One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin. | 02-26-2015 |
20150061040 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 03-05-2015 |
20150064863 | MASKLESS DUAL SILICIDE CONTACT FORMATION - Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a top portion of the second set of epitaxial source/drain regions into a metal silicide and the sacrificial epitaxial layer into a sacrificial silicide layer in a silicidation process wherein the first set of epitaxial source/drain regions underneath the sacrificial epitaxial layer is not affected by the silicidation process; removing selectively the sacrificial silicide layer; and converting a top portion of the first set of epitaxial source/drain regions into another metal silicide. | 03-05-2015 |
20150069532 | METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS USING A REPLACEMENT GATE PROCESS AND THE RESULTING DEVICES - One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction. | 03-12-2015 |
20150111373 | REDUCING GATE HEIGHT VARIATION IN RMG PROCESS - A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates. | 04-23-2015 |
20150129970 | METHODS AND STRUCTURES FOR ELIMINATING OR REDUCING LINE END EPI MATERIAL GROWTH ON GATE STRUCTURES - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 05-14-2015 |
20150145041 | SUBSTRATE LOCAL INTERCONNECT INTEGRATION WITH FINFETS - A substrate local interconnect structure and method is disclosed. A buried conductor is formed in the insulator region or on the semiconductor substrate. The buried conductor may be formed by metal deposition, doped silicon regions, or silciding a region of the substrate. Metal sidewall portions connect transistor contacts to the buried conductor to form interconnections without the use of middle-of-line (MOL) metallization and via layers. | 05-28-2015 |
20150206885 | DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM - Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions. | 07-23-2015 |
20150221549 | PROCESS METHODS FOR ADVANCED INTERCONNECT PATTERNING - Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography. | 08-06-2015 |
20150221591 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 08-06-2015 |
20150270262 | GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 09-24-2015 |
20150289361 | MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure. | 10-08-2015 |
20150325487 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 11-12-2015 |