Patent application number | Description | Published |
20090085532 | DC-DC CONVERTER - A DC-DC converter providing a DC output voltage at an output node. The DC-DC converter comprises an output stage, a digital controller, and a controller. The output stage comprises a pull-up circuit having a control terminal and coupled between a first fixed voltage and a internal node, a pull-down circuit coupled between the internal node and a second fixed voltage, and a low pass filter coupled between the internal node and the output node. The digital controller is powered by the DC output voltage and adjusts the DC output voltage by controlling the output stage. The controller controls a connection of a feedback path, comprising the digital controller, between the output node and the control terminal according to the DC output voltage. | 04-02-2009 |
20090167369 | LVDS OUTPUT DRIVER - An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors. | 07-02-2009 |
20090296869 | COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL - A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration. | 12-03-2009 |
20090296870 | COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING - A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal. | 12-03-2009 |
20100277245 | PHASE LOCK LOOP CIRCUITS - A phase lock loop circuit is provided. A phase frequency detector detects a phase difference between a feedback signal and a reference signal, and generates a phase error signal in response to the detected phase difference. A charge pump consists of at least one core device and outputs a current signal based on the phase error signal. An active loop filter receives and transfers the current signal into a control signal. Operating voltage of the active loop filter is higher than operating voltage of the charge pump. A controlled oscillator receives the control signal and generates an output signal in response to the control signal. A feedback divider receives the output signal to generate the feedback signal. | 11-04-2010 |
20100332887 | STORAGE CONTROL DEVICE HAVING CONTROLLER OPERATED ACCORDING TO DETECTION SIGNAL DERIVED FROM MONITORING POWER SIGNAL AND RELATED METHOD THEREOF - One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range. | 12-30-2010 |
20110043179 | DC-DC Converter - A DC-DC converter providing a DC output voltage at an output node. The DC-DC converter comprises an output stage, a digital controller, and a controller. The output stage comprises a pull-up circuit having a control terminal and coupled between a first fixed voltage and a internal node, a pull-down circuit coupled between the internal node and a second fixed voltage, and a low pass filter coupled between the internal node and the output node. The digital controller is powered by the DC output voltage and adjusts the DC output voltage by controlling the output stage. The controller controls a connection of a feedback path, comprising the digital controller, between the output node and the control terminal according to the DC output voltage. | 02-24-2011 |
20110063002 | BIAS CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT USING THE SAME - A bias circuit for generating an output bias current includes a first transistor, a passive component, a second transistor, and a bias current generator. The first transistor has a first node coupled to a first reference voltage, a second node, and a control node. The passive component is coupled between the first reference voltage and the control node of the first transistor. The second transistor has a first node coupled to the control node of the first transistor, a control node coupled to the second node of the first transistor, and a second node for providing the output bias current according to a current passing through the passive component. The bias current generator is coupled to the second node of the first transistor, and implemented for providing the first transistor with a bias current. | 03-17-2011 |
20140111257 | FREQUENCY DIVIDER, CLOCK GENERATING APPARATUS, AND METHOD CAPABLE OF CALIBRATING FREQUENCY DRIFT OF OSCILLATOR - A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus. | 04-24-2014 |