Shiu

Brian K. Shiu US

Patent application number	Description	Published
20110152890	Devices, Tools and Methods for Performing Minimally Invasive Abdominal Surgical Procedures - Methods, systems, devices and assemblies are provided for treating a patient by: making an incision or puncture though the patient's skin over the abdominal cavity; establishing an initial tract through an opening formed by the incision or puncture; advancing an instrument through the tract; contacting a distal end portion of the instrument against an inner surface of the abdominal cavity; driving at least one stitching needle through the inner surface of the abdominal cavity; continuing the driving until the at least one stitching needle exits the inner surface of the abdominal cavity; anchoring a suture carried by each of the at least one stitching needle to a suture anchor at an exit location, respectively; and applying tension to each of the sutures.	06-23-2011
20110172767	MINIMALLY INVASIVE, DIRECT DELIVERY METHODS FOR IMPLANTING OBESITY TREATMENT DEVICES - A method includes selecting a template from a plurality of different sizes of templates based on measurements of the abdominal cavity of a patient; orienting the template on the patient at a location overlying the abdominal cavity to select an appropriate size implant using fluoroscopic imaging; marking an incision location and an indicator of an angle of approach; and removing the template from the patient, wherein marks made by the marking remain on the patient. Methods apparatus, instruments and implants for treating a patient are provided.	07-14-2011

Chih Bun Shiu, Hong Kong CN

Patent application number	Description	Published
20120002441	AREA LIGHT SOURCE DEVICE - An area light source device has a diffusion plate and a prism sheet stacked on a light guide plate, and a light source disposed opposite an end face of the light guide plate. Light emitted from the light source is introduced to an inside of the light guide plate from the end face. Area light emission is obtained by outputting the light diffused in the light guide plate from the diffusion plate and the prism sheet through a front face disposed opposite the diffusion plate. The light guide plate includes a light guide section that includes the end face disposed opposite the light source, a light emitting section that is disposed opposite the diffusion plate, and a joining section that joins the light guide section and the light emitting section. The front surface in the joining section includes an inclined surface that is gradually retreated toward a rear surface on an opposite side from the light guide section toward the light emitting section. The front faces of the light guide section and the joining section are covered with a light shielding member. The light shielding member is fixed to the diffusion plate without interposing the prism sheet therebetween. The light shielding member and the inclined surface are arranged to allow air to be interposed therebetween.	01-05-2012

Da-Shan Shiu, Taipei City TW

Patent application number	Description	Published
20150098376	METHODS FOR ONE RADIO MODULE TO LISTEN TO PAGING SIGNALS WITHOUT BREAKING THE DATA TRANSMISSION OF THE OTHER RADIO MODULE OPERATING IN THE CONNECTED MODE AND COMMUNICATION APPARATUSES UTILIZING THE SAME - A communications apparatus. A first radio module communicates with a first wireless network and provides wireless communication services in compliance with a first RAT. A second radio module communicates with a second wireless network and provides wireless communication services in compliance with a second RAT. At least two antennas are shared by the first radio module and the second radio module. When the first radio module operates in an idle mode and when the timing of the first radio module performing a first receiving activity coincides with the timing of the second radio module performing a second receiving activity, the second radio module uses the antennas to perform the second receiving activity when a DRX cycle duration of the first radio module in the idle mode is shorter than a DRX cycle duration of the second radio module.	04-09-2015
20150257090	METHODS FOR ONE RADIO MODULE TO LISTEN TO PAGING SIGNALS WITHOUT BREAKING THE DATA TRANSMISSION OF THE OTHER RADIO MODULE OPERATING IN THE CONNECTED MODE AND COMMUNICATION APPARATUSES UTILIZING THE SAME - A communications apparatus. A first radio module communicates with a first wireless network and provides wireless communications services. A second radio module communicates with a second wireless network and provides wireless communications services. At least two antennas shared by the first radio module and the second radio module. When the first radio module operates in a connected mode and when the timing of the first radio module performing the first receiving activity coincides with the timing of the second radio module performing a second receiving activity, the first radio module reports a value of 1 for a Rank Indicator to the first wireless network at least once before the second radio module is to perform the second receiving activity, and then the second radio module uses one of the antennas to perform the second receiving activity.	09-10-2015
20160124499	SYSTEMS AND METHODS FOR PROCESSING INCOMING EVENTS WHILE PERFORMING A VIRTUAL REALITY SESSION - A virtual reality (VR) system including a virtual reality display and a virtual reality host is provided. The virtual reality display is arranged for displaying a virtual environment for a virtual reality user. The virtual reality host is arranged for performing a virtual reality session to generate the virtual environment using the virtual reality display and creating a virtual interface to sync and interact with a source unit, wherein when the source unit receives an incoming event, the virtual reality host receives a notification regarding the incoming event from the source unit and provides the notification to the virtual interface to generate an alert for the notification to the screen of the virtual reality display in the virtual environment for the virtual reality user.	05-05-2016

Hao Shiu, Puli TW

Patent application number	Description	Published
20160097107	METHOD FOR PRODUCING MONOSACCHARIDES FROM ALGAE - A method for producing monosaccharides from algae includes (a) treating algae-containing water using an electrocoagulation device having an iron-based anode to induce flocculation of algae so as to obtain flocculated algae which have a trace amount of iron derived from the iron-based anode, (b) collecting the flocculated algae from the algae-containing water, and (c) subjecting the flocculated algae to an acid hydrolysis reaction in an acid solution to obtain monosaccharides. A liquid-to-solid ratio of a volume of the acid solution to a solid content of the flocculated algae is not less than 12 ml/g. The acid solution has an acid concentration not less than 3% by volume.	04-07-2016

Hei-Ming Shiu, Hong Kong HK

Patent application number	Description	Published
20120181678	LEADLESS CHIP CARRIER HAVING IMPROVED MOUNTABILITY - Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.	07-19-2012

Herbert Shiu, Lai Chi Kok HK

Patent application number	Description	Published
20150293946	CROSS MODEL DATUM ACCESS WITH SEMANTIC PRESERVATION FOR UNIVERSAL DATABASE - Cross database model datum access with semantic preservation is provided. Data stored in a database under a particular database model can typically be inaccessible or not interoperable with data stored in another database model. A first datum of a first database model is transformed to an interim datum of an interim database model while preserving the data semantics associated with the first datum. Further, the second datum can be transformed into a third datum associated with a third database model, again while preserving the semantics. As such, data in a first silo can be accessed in a different silo while retaining semantic relationships. Further, the use of an interim database can reduce the processing needed to accomplish transforms between a planarity of database models.	10-15-2015

Jian-Feng Shiu, Zhubei City TW

Patent application number	Description	Published
20150381179	SIGNAL TRANSMISSION CIRCUIT SUITABLE FOR DDR - A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage.	12-31-2015

Jin-Feng Shiu, Hsinchu City TW

Patent application number	Description	Published
20160023901	METHOD AND APPARATUS FOR RECYCLING WASTE SULFURIC ACID - A method and an apparatus for recycling waste sulfuric acid solution are provided. The method includes providing a reaction tank and introducing a waste sulfuric acid (H	01-28-2016

Kin Wah Shiu, Kwun Tong HK

Patent application number	Description	Published
20140174636	METHOD FOR FABRICATING DECORATIVE COLORED GLASS - Disclosed is a method for fabricating a piece of decorative colored glass, which comprises the following steps: covering a layer of protective film which has a pre-fabricated pattern that can be removed on a piece of glass; removing the pattern from the protective film; sand blasting the surface of the glass that the pattern is removed; cleaning the glass that is sand blasted; and coating oil on the surface of the glass where is sand blasted to obtain the decorative colored glass. The glass fabricated by the method of this invention can represent a stereoscopic impression through observation, which color may not be changed and discolored.	06-26-2014

Kuen-Ting Shiu, White Plains, NY US

Patent application number	Description	Published
20110186910	METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH - There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.	08-04-2011
20120060905	NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS - A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.	03-15-2012
20120132913	III-V Compound Semiconductor Material Passivation With Crystalline Interlayer - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.	05-31-2012
20120187505	Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.	07-26-2012
20120193687	REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF n+ Ge - Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.	08-02-2012
20120248535	SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET) AND INTEGRATED CIRCUIT (IC) CHIP - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.	10-04-2012
20120261718	Method And Structure For Compound Semiconductor Contact - The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.	10-18-2012
20120285520	WAFER BONDED SOLAR CELLS AND FABRICATION METHODS - A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.	11-15-2012
20120318338	NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS - A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.	12-20-2012
20120318342	UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.	12-20-2012
20120322244	METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.	12-20-2012
20130001657	SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.	01-03-2013
20130001659	SELF-ALIGNED III-V MOSFET DIFFUSION REGIONS AND SILICIDE-LIKE ALLOY CONTACT - A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.	01-03-2013
20130005119	METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.	01-03-2013
20130048061	MONOLITHIC MULTI-JUNCTION PHOTOVOLTAIC CELL AND METHOD - A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate.	02-28-2013
20130071999	HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS - A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.	03-21-2013
20130082303	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.	04-04-2013
20130082356	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.	04-04-2013
20130153964	FETs with Hybrid Channel Materials - Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.	06-20-2013
20130168834	III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER - The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.	07-04-2013
20130175633	CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS - A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.	07-11-2013
20130200443	Interface Engineering to Optimize Metal-III-V Contacts - Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.	08-08-2013
20130270608	HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.	10-17-2013
20130292801	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A semiconductor structure is provided that includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.	11-07-2013
20130295750	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A method of removing a plurality of semiconductor device layers from an underlying base substrate. A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. Each successive sacrificial material layer that is formed is thicker than the previously formed sacrificial material layer. An etch is then performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.	11-07-2013
20130307089	Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.	11-21-2013
20130309830	Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.	11-21-2013
20130316538	SURFACE MORPHOLOGY GENERATION AND TRANSFER BY SPALLING - The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns.	11-28-2013
20140024222	HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS - A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.	01-23-2014
20140091370	TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.	04-03-2014
20140094006	TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.	04-03-2014
20140124033	UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.	05-08-2014
20140131722	DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON - A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A dual phase gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure.	05-15-2014
20140131724	SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure.	05-15-2014
20140131770	CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.	05-15-2014
20140134811	CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.	05-15-2014
20140134830	SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A method for selective formation of a gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure.	05-15-2014
20140138781	DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES - A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.	05-22-2014
20140191283	GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES - A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.	07-10-2014
20140191284	GROUP III NITRIDES ON NANOPATTERNED SUBSTRATES - A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.	07-10-2014
20140217468	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.	08-07-2014
20140220766	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.	08-07-2014
20140264446	III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.	09-18-2014
20140264607	III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.	09-18-2014
20140315389	CRACK CONTROL FOR SUBSTRATE SEPARATION - A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.	10-23-2014
20140332851	REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.	11-13-2014
20140332855	REDUCED SHORT CHANNEL EFFECT OF III-V FIELD EFFECT TRANSISTOR VIA OXIDIZING ALUMINUM-RICH UNDERLAYER - In one embodiment, a method of forming a semiconductor device is provided that may include forming a semiconductor device including a gate structure on a channel portion of III-V semiconductor substrate. The III-V semiconductor substrate including a III-V base substrate layer, an aluminum containing III-V semiconductor layer that is present on the III-V base substrate layer, and a III-V channel layer. Oxidizing a portion of the aluminum containing III-V semiconductor layer on opposing sides of the gate structure. Forming a raised source region and a raised drain region over the portion of the aluminum containing III-V semiconductor layer that has been oxidized. Forming interconnects to the raised source region and the raised drain region.	11-13-2014
20140367745	T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.	12-18-2014
20140370683	T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.	12-18-2014
20150014778	MULTIPLE VIA STRUCTURE AND METHOD - A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.	01-15-2015
20150030047	III-V LASERS WITH INTEGRATED SILICON PHOTONIC CIRCUITS - III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.	01-29-2015
20150048422	A METHOD FOR FORMING A CRYSTALLINE COMPOUND III-V MATERIAL ON A SINGLE ELEMENT SUBSTRATE - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.	02-19-2015
20150048423	SEMICONDUCTOR DEVICE HAVING A III-V CRYSTALLINE COMPOUND MATERIAL SELECTIVELY GROWN ON THE BOTTOM OF A SPACE FORMED IN A SINGLE ELEMENT SUBSTRATE. - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.	02-19-2015
20150115369	CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.	04-30-2015
20150140831	CRACK CONTROL FOR SUBSTRATE SEPARATION - A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.	05-21-2015
20150235838	HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (	08-20-2015
20150235903	Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation - A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.	08-20-2015
20150255281	SILICON SUBSTRATE PREPARATION FOR SELECTIVE III-V EPITAXY - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.	09-10-2015
20150280023	UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.	10-01-2015
20150287790	SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON - A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.	10-08-2015
20150311179	TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.	10-29-2015
20150325682	PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL - A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.	11-12-2015
20160072002	NANOWIRES FORMED BY EMPLOYING SOLDER NANODOTS - A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.	03-10-2016

Kuen-Ting Shiu, Ann Arbor, MI US

Patent application number	Description	Published
20090095349	TYPE II QUANTUM DOT SOLAR CELLS - A device comprises a plurality of fence layers of a semiconductor material and a plurality of alternating layers of quantum dots of a second semiconductor material embedded between and in direct contact with a third semiconductor material disposed in a stack between a p-type and n-type semiconductor material. Each quantum dot of the second semiconductor material and the third semiconductor material form a heterojunction having a type II band alignment. A method for fabricating such a device is also provided.	04-16-2009
20130237001	METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH - There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.	09-12-2013

Kuen-Ting Shiu US

Patent application number	Description	Published
20120248501	SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.	10-04-2012
20120248502	III-V FIELD EFFECT TRANSISTOR (FET) AND III-V SEMICONDUCTOR ON INSULATOR (IIIVOI) FET, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.	10-04-2012

Kuen-Ting Shiu, White Plalins, NY US

Patent application number	Description	Published
20130264658	Reduced S/D Contact Resistance of III-V Mosfet Using Low Temperature Metal-Induced Crystallilzation of n+ Ge - Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.	10-10-2013

Kuen-Ting Shiu, Yorktown Heights, NY US

Patent application number	Description	Published
20140374800	OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.	12-25-2014
20140377918	OVERLAPPED III-V FINFET WITH DOPED SEMICONDUCTOR EXTENSIONS - A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.	12-25-2014
20150243773	III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS - A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.	08-27-2015
20150255460	COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR STRUCTURE WITH III-V AND SILICON GERMANIUM TRANSISTORS ON INSULATOR - Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET.	09-10-2015
20150262818	PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER - A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.	09-17-2015
20150279696	Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping - The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.	10-01-2015
20150325650	III-V SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACTS - A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.	11-12-2015
20160087160	III-V PHOTONIC INTEGRATED CIRCUITS ON SILICON SUBSTRATE - A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.	03-24-2016
20160103278	COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIALLY FORMED MATERIAL - An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic tight detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.	04-14-2016
20160105247	COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH III-V OPTICAL INTERCONNECT HAVING III-V EPITAXIAL SEMICONDUCTOR MATERIAL FORMED USING LATERAL OVERGROWTH - An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.	04-14-2016

Kuen-Ting R. Shiu, Ann Arbor, MI US

Patent application number	Description	Published
20080219662	Monolithically Integrated Reconfigurable Optical Add-Drop Multiplexer - A reconfigurable optical add-drop mulitplexer comprises a first waveguide layer having formed therein a first multiplexer-demultiplexer, a second multiplexer-demultiplexer, and a plurality of optical switches. The reconfigurable optical add-drop multiplexer further comprises a second waveguide layer optically coupled to the first waveguide and having a second effective index of refraction, said second waveguide layer having an optical amplifier formed therein. An input signal is amplified by the optical amplifier and communicated to the first optical multiplexer-demultiplexer where the signal is demultiplexed into a plurality individual wavelength signals. The second optical multiplexer-demultiplexer is adapted to receive a multiplexed add signal and to demultiplex the add signal into component wavelength signals. The individual wavelength signals are received at the optical switches and selectively routed to either an optical detector or toward the first multiplexer-demultiplexer. The individual wavelength signals received at the first multiplexer-demultiplexer are multiplexed into an output signal.	09-11-2008

Lai Sheung Shiu, Happy Valley HK

Patent application number	Description	Published
20100139160	Plant pot having soil moisture audio alarm - A plant pot having a built-in soil moisture audio alarm that provides a caretaker of the plant pot with an audio alarm when the moisture in the soil in the plant pot falls below a prescribed level.	06-10-2010

Leung M. Shiu, Gaithersburg, MD US

Patent application number	Description	Published
20140271087	SYSTEM AND METHOD OF AUTOMATIC FEEDER STACK MANAGEMENT - Embodiments of a system and method for singulating articles in an automatic stack feeder are disclosed. The automatic stack feeder may comprise a pressure sensor on a perforated drive belt assembly configured to sense the pressure exerted by a stack of articles. The sensed pressure may be used to control various portions of the automatic stack feeder, such as a belt or a paddle.	09-18-2014
20140271089	SYSTEM AND METHOD OF UNLOADING A CONTAINER OF ITEMS - Embodiments of a system and method for unloading articles from a container of items for use in an automatic stack feeder are disclosed. The automatic stack feeder may comprise a belt, a moveable lower paddle, and a moveable upper paddle, wherein the lower paddle is configured to partially extend through a belt of the automatic stack feeder. The movement of the belt, the lower paddle, and the upper paddle are coordinated such that there is no need to interrupt the operation of the automatic stack feeder to unload the container.	09-18-2014
20140271090	SYSTEM AND METHOD OF ARTICLE FEEDER OPERATION - Embodiments of a system and method for shingulating, singulating, and synchronizing articles in an article feeder system are disclosed. The article feeder system may include a shingulating device configured to receive a stack of articles and to produce a positively lapped stack of articles, a plurality of picking devices configured to pick one or more articles from the positively lapped stack of articles and to produce one or more singulated articles, and one or more synchronization devices configured to deliver the one or more singulated articles to one or more sorter windows.	09-18-2014
20140271091	ANTI-ROTATION DEVICE AND METHOD OF USE - A device for reducing rotation of an article during singulation of a stack of articles is disclosed. The device may include a torsion element, a rotatable member configured to rotate about an elongated axis of the torsion element between a first position and a second position, and a revolving member coupled to the rotatable member. An outer surface of the revolving member contacts a drive belt in the first position and an article in the second position. The torsion element exerts torque on the rotatable member when it moves from the first position towards the second position. The torque causes the outer surface of the revolving member to apply a frictional force to the article, thereby minimizing rotation of the article. Systems and methods of singulating articles are also disclosed.	09-18-2014
20150144765	SYSTEM AND METHOD FOR IMPROVED FIXATION OF FLATS SEQUENCING SYSTEM LINEAR ACTUATOR - A system of mitigating force in a mechanical system, the system comprising a frame member, a first rail connected to the frame member, a second rail connected to the frame member and extending along the frame member in parallel to the first rail, an assembly movably engaging the first and second rails, and a first bracket located between the first and second rails, with at least one first bracket attachment secured to the frame member, the first bracket sharing an upper edge with a lower edge of the first rail, such that a downward force applied on the first rail is distributed to the first bracket and the frame member via the at least one first bracket attachment.	05-28-2015
20150251221	SYSTEM AND METHOD OF UNLOADING A CONTAINER OF ITEMS - Embodiments of a system and method for unloading articles from a container of items for use in an automatic stack feeder are disclosed. The automatic stack feeder may comprise a belt, a moveable lower paddle, and a moveable upper paddle, wherein the lower paddle is configured to partially extend through a belt of the automatic stack feeder. The movement of the belt, the lower paddle, and the upper paddle are coordinated such that there is no need to interrupt the operation of the automatic stack feeder to unload the container.	09-10-2015
20150251862	ANTI-ROTATION DEVICE AND METHOD OF USE - A device for reducing rotation of an article during singulation of a stack of articles is disclosed. The device may include a torsion element, a rotatable member configured to rotate about an elongated axis of the torsion element between a first position and a second position, and a revolving member coupled to the rotatable member. An outer surface of the revolving member contacts a drive belt in the first position and an article in the second position. The torsion element exerts torque on the rotatable member when it moves from the first position towards the second position. The torque causes the outer surface of the revolving member to apply a frictional force to the article, thereby minimizing rotation of the article. Systems and methods of singulating articles are also disclosed.	09-10-2015
20160001985	SYSTEM AND METHOD OF ARTICLE FEEDER OPERATION - Embodiments of a system and method for shingulating, singulating, and synchronizing articles in an article feeder system are disclosed. The article feeder system may include a shingulating device configured to receive a stack of articles and to produce a positively lapped stack of articles, a plurality of picking devices configured to pick one or more articles from the positively lapped stack of articles and to produce one or more singulated articles, and one or more synchronization devices configured to deliver the one or more singulated articles to one or more sorter windows.	01-07-2016

Li-Sheng Shiu, Taoyuan City TW

Patent application number	Description	Published
20160141094	TRANSFORMER AND BOBBIN THEREOF - A bobbin is provided. The bobbin includes a base, a first pin unit and a second pin unit. The base includes a first surface, a first side and a second side. The first pin unit is connected to the first side. The first pin unit includes a first connection portion. The first connection portion is connected to the base. The first connection portion includes a first enhancing structure. The first enhancing structure protrudes from the first surface, the first enhancing structure includes a first lateral wall. The first lateral wall is connected to the first surface. A first boundary line exists where the first lateral wall is connected to the first surface, and the first boundary line is not a straight line. The second pin unit is connected to the second side.	05-19-2016

Ming-Shu Shiu, Kinmen County TW

Patent application number	Description	Published
20150239430	REMOTE ANTI-THEFT SYSTEM FOR VEHICLES - A remote anti-theft system for vehicles is revealed. It comprises an anti-theft system having a processing unit and a power supply unit, wherein the processing unit is provided with a petrol reduction processing unit for controlling an engine to gradually reduce an amount of injected petrol and is connected with a wireless signal transmission unit for satellite positioning and wireless communication with a predetermined communication device.	08-27-2015

Patrick Shiu, Vancouver CA

Patent application number	Description	Published
20110301978	SYSTEMS AND METHODS FOR MANAGING PATIENT MEDICAL INFORMATION - Methods and systems for managing patient medical information are provided in order to make it more convenient for patient information to be managed both electronically and using traditional physical files. The methods and systems comprise: storing patient medical information in an electronic patient record; generating at least one adhesive medical summary corresponding to the patient medical information; and, affixing the adhesive medical summary to a physical patient record. An electronic patient record may be stored in a database and may comprise general patient identifier information, patient assessment or medical examination information, patient prescription information, and/or immunization information. The methods and systems may also comprise billing information that may be used to generate billing summaries. Medical condition templates comprising default medical assessment information as typically determined for a specific medical condition may be used to facilitate the entry of patient medical information.	12-08-2011

Ruei-Shiue Shiu, Kaohsiung TW

Patent application number	Description	Published
20150332146	DEVICE AND METHOD FOR COMPARISON OF MULTIPLE TROPICAL CYCLONE ROUTES - The present invention relates to a method for comparison of multiple tropical cyclone routes. The method is implementable through a mobile device having an application processor and a touch-sensed display. The method is capable of determining multiple reference cyclone routes relevant to an concerned cyclone route by comparing each of multiple historical cyclone routes, each of which routes consists of multiple cyclone center coordinates, with an estimated cyclone route consisting of multiple estimated cyclone center coordinates for representing the concerned cyclone route.	11-19-2015

Shih-Je Shiu, Huwei Township TW

Patent application number	Description	Published
20160129539	BACKLASH AUTOMATIC DETECTION SYSTEM AND METHOD USING THE SAME - A backlash automatic detection system comprises a control device and a machine tool. The machine tool comprises a servo driver, a lead screw, a nut seat and a platform. The method comprises: entering an initial state and outputting a control command to the servo driver through the control device; driving the lead screw by the servo driver to move the nut seat towards a first direction and changing the movement direction of the nut seat towards a reverse second direction by the servo driver; defining a backlash phenomenon period according to one time point at which the nut seat starts to move towards the second direction and another time point at which the platform is driven to move by the nut seat; defining the displacement of the nut seat corresponding to the backlash phenomenon period as a backlash value.	05-12-2016
20160132038	MACHINING ASSISTANCE METHOD AND THE APPARATUS USING THE SAME - A machining assistance method and an apparatus using the same are provided. The machining assistance method comprises following steps. Firstly, a circle correction path is received for driving a platform to perform a circular motion. Next, a driving torque of the server driver driving the platform is obtained. Then, whether the driving torque is changed to 0 is determined; if yes, a first position of the platform is recorded. Then, whether the driving torque is changed to a peak is determined; if yes, a second position of the platform is recorded. After that, the server driver is controlled to drive the platform according to a first position and a second position in a machining process.	05-12-2016

Shih-Je Shiu, Chutung TW

Patent application number	Description	Published
20160132039	CUTTING TOOL CONTROLLER AND METHOD OF CONTROLLING THE SAME - A cutting tool controller and method of controlling are provided. The method includes providing a swing angle for the cutting tool, obtaining a swing vector of the cutting tool through kinematics calculation according to the swing angle, using the swing vector of the cutting tool to calculate a set of possible solutions of a swaying angle of the cutting tool, selecting a possible solution satisfying an operation condition of the machine from the set of possible solutions, using the selected possible solution to calculate an offset of positions of the cutting tool before and after swaying, so as to generate a compensation vector, calculating required compensation values for three axes of the machine according to the compensation vector, and outputting a control command including the compensation values, such that the cutting tool of the machine or a working table for placing the workpiece thereon of the machine moves correspondingly.	05-12-2016

Shu-Ping Shiu, Tainan City TW

Patent application number	Description	Published
20150200692	SYSTEM FOR THE COEXISTENCE BETWEEN A PLURALITY OF WIRELESS COMMUNICATIONS MODULES SHARING SINGLE ANTENNA - A system for the coexistence between a plurality of wireless communication modules sharing a single antenna includes an antenna, first and second transceiving paths, and first and second wireless communications modules. The first wireless communications module is coupled to a first transceiving path and transmits or receives first wireless signals via the first transceiving path. The second wireless communications module is coupled to the second transceiving path and transmits and receives second wireless signals via the first and the second transceiving paths, wherein signal strengths of the second wireless signals passing through the second transceiving path are attenuated by a certain level, and the attenuated second wireless signals are added to the first wireless signals when passing through the first transceiving path, wherein one of the first and the second communications module is a LTE module and the other one is a WLAN module.	07-16-2015

Simon Kai-Ying Shiu, Bristol GB

Patent application number	Description	Published
20080270198	Systems and Methods for Providing Remediation Recommendations - In one embodiment, a system and method pertain to receiving audit exceptions indicative of instances of noncompliance of an information system under evaluation relative to a policy or standard, identifying remediation recommendations that are relevant to the audit exceptions and that indicate how to correct conditions that caused the noncompliance, and providing the remediation recommendations to an entity responsible for correcting the conditions so as to provide information as to how the information system can be brought into compliance with the policy or standard.	10-30-2008
20120110670	SYSTEM AND METHOD FOR ANALYZING A PROCESS - A system for analyzing a process, comprising a model engine to generate a model of the environment using multiple components defining adjustable elements of the model and including components representing a process for provisioning and de-provisioning of access credentials for an individual in the environment and a risk analyzer to calculate multiple randomized instances of an outcome for the environment using multiple values for parameters of the elements of the model selected from within respective predefined ranges for the parameters, and to use a results plan to provide data for identifying the security risk using the multiple instances.	05-03-2012
20120179501	DECISION SUPPORT - Information relating to an entity's objectives is received, a utility function based on the received objectives is derived, the utility function is compared with results from a number of simulated investment options, and the comparisons are presented to a user associated with the entity.	07-12-2012
20160125201	HARDWARE-PROTECTIVE DATA PROCESSING SYSTEMS AND METHODS USING AN APPLICATION EXECUTING IN A SECURE DOMAIN - A data processing system supporting a secure domain and a non-secure domain comprises a hardware component, and a processor device having operating modes in the secure domain and non-secure domain, the processor device to execute a secure application in the secure domain. The hardware component has a property having a secure state. The property of the hardware component in the secure state may only be reconfigured responsive to instructions received from the secure domain. The secure application is operative to implement a configuration service to configure the property of the hardware component in the secure state, responsive to a request received from the non-secure domain according to an application programming interface associated with the secure application.	05-05-2016
20160127128	MANAGEMENT OF CRYPTOGRAPHIC KEYS - An electronic device for management of cryptographic keys, and a corresponding method implemented in a computing device comprising a physical processor, transmit feature data of the device to a key generation module, wherein the feature data comprises information corresponding to an identifier or an attribute of the device, and receive, by the device from the key generation module, a digital signature of the transmitted feature data. The device installs the received digital signature as a cryptographic private key for communication, and performs a cryptographic operation using the installed digital signature as the cryptographic private key.	05-05-2016

Simon Kai-Ying Shiu, Bristok GB

Patent application number	Description	Published
20080271110	Systems and Methods for Monitoring Compliance With Standards or Policies - In one embodiment, a system or method pertain to accessing a model that comprises a computer-readable version of a standard or policy, identifying rules or requirements specified by the model that pertain to compliance with the standard or policy, and automatically generating questions relevant to the identified rules or requirements, the questions being intended to query intended respondents as to compliance with the identified rules or requirements.	10-30-2008

Simon K.y. Shiu, Bristol GB

Patent application number	Description	Published
20120110669	METHOD AND SYSTEM FOR ANALYZING AN ENVIRONMENT - A system for analyzing an environment to identify a security risk, comprising a model engine to generate a model of the environment using multiple components defining adjustable elements of the model and a risk analyzer to calculate multiple randomized instances of an outcome for the environment using multiple values for parameters of the elements of the model selected from within respective predefined ranges for the parameters.	05-03-2012

Stephen Yuen Wing Shiu, Hong Kong HK

Patent application number	Description	Published
20090062189	TUMOR SUPPRESSOR PROTEIN AND NUCLEOTIDE ENCODING SAME - The invention provides a method for suppressing tumor cell growth in a patient, comprising: administering to the patient an effective amount of an expression vector including a polynucleotide encoding a tumor suppressor protein having SEQ ID NO: 1 under conditions wherein the expression vector incorporates itself into the tumor cell genome and inhibits cell proliferation or induces cell death.	03-05-2009

Teddie Shiu, Markham CA

Patent application number	Description	Published
20110301978	SYSTEMS AND METHODS FOR MANAGING PATIENT MEDICAL INFORMATION - Methods and systems for managing patient medical information are provided in order to make it more convenient for patient information to be managed both electronically and using traditional physical files. The methods and systems comprise: storing patient medical information in an electronic patient record; generating at least one adhesive medical summary corresponding to the patient medical information; and, affixing the adhesive medical summary to a physical patient record. An electronic patient record may be stored in a database and may comprise general patient identifier information, patient assessment or medical examination information, patient prescription information, and/or immunization information. The methods and systems may also comprise billing information that may be used to generate billing summaries. Medical condition templates comprising default medical assessment information as typically determined for a specific medical condition may be used to facilitate the entry of patient medical information.	12-08-2011

Tzyuan Shiu, Taipei City TW

Patent application number	Description	Published
20150055691	COMMUNICATION CIRCUIT AND ASSOCIATED METHOD FOR CALIBRATING COMMUNICATION CIRCUIT - The present invention provides a method for calibrating a communication circuit. In an embodiment, the method may include: cooperating start of a calibration procedure, and, by the communication circuit, signaling a calibration signal between a test equipment and the communication circuit. The calibration signal may include a plurality of coexisting component signals respectively at a plurality of calibration frequencies. Associated communication circuit is also disclosed.	02-26-2015

Wen-Bing Shiu, Potomac Falls, VA US

Patent application number	Description	Published
20080253771	Method and apparatus for configuring Optical Network Terminals (ONT) in a network - A method and system allowing a network operator to change services on a large group of Optical Network Terminals (ONTs) at one time through the use of profiles. At least one profile is configured, and at least one of the profiles is associated with at least one Optical Network Terminal (ONT) having a number of ports. A configuration for the ONTs is generated based on the profiles and, upon a request by an ONT, the configuration is forwarded to the requesting ONT. The method and system may include a graphical user interface (GUI) for entering information used in configuring the profiles, and may assign the profiles to multiple ONTs. Further, the GUI may automatically gather and provide statistics relating to the ONTs to the network operator. Additionally, in a Session Initiation Protocol (SIP) network, the method and system may communicate with the ONTs without using a SIP protocol stack.	10-16-2008
20090067415	Optical network terminal with integrated internet protocol private branch exchange - Internet Protocol (IP) private branch exchange (IP-PBX) functionality may be provided on existing optical network terminal (ONT) hardware without support of an IP-PBX device by using a method of managing an IP-PBX that includes identifying IP configuration data on downstream network communications associated with at least one private IP branch exchange service received from an upstream node on a session initiation protocol (SIP) network and applying the configuration data to a node in an access network that supports the IP-PBX service. In this way, centralized configuration of IP-PBX services are supported, simplifying network management for service providers.	03-12-2009

Winnie Shiu, Middlesex GB

Patent application number	Description	Published
20100222426	Anti-Bacterial Agents - The invention relates to novel acylphloroglucinols which have strong growth inhibitory effects on multi-drug resistant strains of bacteria, particularly MRSA. Typically the compounds have a terpene substituent, or a terpene-derived substituent. Methods of isolating the compounds from natural sources, and synthetic methods for forming the compounds are also provided.	09-02-2010

Ya-Li Shiu, Neipu TW

Patent application number	Description	Published
20160135483	Aquaculture feed formed from fermented soybean meal and earthworm meal, including the fermentation preparation method for the mixture ingredient - A method for producing a fermented aquaculture feed includes forming a powder mixture of soybean meal and earthworm meal, adding water to the powder mixture to form a first feed mixture, adding a culture of	05-19-2016

Yao-Wen Shiu, Taoyuan County TW

Patent application number	Description	Published
20150162515	ELECTRONIC APPARATUS AND PROTECTIVE COVER OF MOBILE DEVICE - An electronic apparatus and a protective cover for a mobile device are disclosed. The protective cover is removably attached on an outer surface of a mobile device. The protective cover comprises an outer protective layer, a thermo-conductive layer and a thermoelectric material layer. The thermo-conductive layer is attached on the outer surface of the mobile device. The thermoelectric material layer has a first side adjacent to the thermo-conductive layer and a second side adjacent to the outer protective layer. The thermoelectric material layer generates a current according to a temperature difference between the first side and the second side.	06-11-2015

Yi-Min Shiu, Chupei City TW

Patent application number	Description	Published
20160020825	INPUT/OUTPUT SIGNAL PROCESSING CIRCUIT AND INPUT/OUTPUT SIGNAL PROCESSING METHOD - The present invention discloses an input/output (I/O) signal processing circuit and processing method. The I/O signal processing circuit includes a level adjustable I/O circuit and an adjustment circuit. The I/O signal processing circuit includes an output driver and/or an input comparator. The output driver transmits an output signal via a signal transmission line according to an output data. The output driver has an adjustable high operation voltage level and an adjustable low operation voltage level, which determine a high level and a low level of the output signal, respectively. The input comparator receives an input signal via the signal transmission line and comparing the input signal with an adjustable reference voltage, so as to generate an input data. The adjustment circuit generates an adjustment signal according to voltage drop related information, to correspondingly adjust the adjustable high and low operation voltage level and/or the adjustable reference voltage.	01-21-2016

Yi-Min Shiu, Hsinchu TW

Patent application number	Description	Published
20150372601	POWER SUPPLY SYSTEM AND SHORT CIRCUIT AND/OR BAD CONNECTION DETECTION METHOD THEREOF, AND POWER CONVERTER THEREOF - The present invention discloses a short circuit and/or bad connection detection method for use in a power supply system. The power supply system includes a power converter which converts an input voltage to an output voltage and supplies an output current to an electronic device. In the short circuit detection method, the conversion from the input voltage to the output voltage is disabled in a disable time period, and whether a short circuit occurs is determined according to the decreasing speed of the output voltage. In the bad connection detection method, an actual voltage and an actual current received by the electronic device are compared with the output voltage and the output current, to determine whether a bad connection occurs.	12-24-2015
20160033566	ABNORMAL CONNECTION DETECTION METHOD - An abnormal connection detection method is used between a power supplier and a power receiver. The power supplier and the power receiver are connected through a cable. The cable includes positive and negative power transmission lines. The abnormal connection detection method includes: providing an output voltage from the power supplier, wherein the output voltage is lower than a predetermined voltage threshold; detecting, according to the output voltage, whether an output current generated by the power supplier is higher than a predetermined current threshold; and when the output current is higher than the predetermined current threshold, determining that an abnormal connection occurs between the power supplier and the power receiver.	02-04-2016

Yi-Sheng Shiu, Taichung City TW

Patent application number	Description	Published
20160085988	Management Method and Computer System Thereof - A management method for a cloud server system is disclosed. The management method includes accepting registering of a first administer account and a preserved account; and permitting uploading or editing at least one individual information via the first administer account for the cloud server system while a user corresponding to the preserved account does not comply with a predetermined principle, or authorizing the user corresponding to the preserved account to upload or edit the at least one individual information for the cloud server system while the user corresponding to the preserved account complies with the predetermined principle; wherein the predetermined principle is a children online privacy limitation, a user corresponding to the first administer account is a legal guardian for the user corresponding to the preserved account, and the at least one individual information represents a personal identification for the user corresponding to the preserved account.	03-24-2016