Patent application number | Description | Published |
20080303567 | DELAY LOCKED LOOP CIRCUIT - A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal. | 12-11-2008 |
20080315933 | PULSE SYNTHESIS CIRCUIT - A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node. | 12-25-2008 |
20090115502 | REFERENCE CURRENT CIRCUIT, REFERENCE VOLTAGE CIRCUIT, AND STARTUP CIRCUIT - A current mirror circuit | 05-07-2009 |
20090134931 | MULTIPHASE LEVEL SHIFT SYSTEM - Each of n level shifters (LS | 05-28-2009 |
20090167400 | DEVICE AND METHOD FOR GENERATING CLOCK SIGNAL - In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector selects one of the multi-phase intermediate clock signals. A second phase selector selects one of the multi-phase clock signals. A latch circuit latches the intermediate clock signal selected by the first phase selector with the clock signal selected by the second phase selector. | 07-02-2009 |
20090237281 | A/D CONVERTER - An A/D converter includes: a plurality of A/D conversion circuits ( | 09-24-2009 |
20090284282 | LEVEL SHIFTER - Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes. | 11-19-2009 |
20100149010 | PIPELINED AD CONVERTER - A pipelined AD converter ( | 06-17-2010 |
20100225518 | DIGITAL/ANALOG CONVERTER CIRCUIT - A selection section ( | 09-09-2010 |
20100271142 | COUPLED RING OSCILLATOR AND METHOD FOR LAYING OUT THE SAME - A coupled ring oscillator includes n ring oscillators ( | 10-28-2010 |
20110080821 | COUPLED RING OSCILLATOR AND METHOD FOR INITIALIZING THE SAME - In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state. | 04-07-2011 |
20110140754 | REFERENCE FREQUENCY GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE - An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. | 06-16-2011 |
20120319880 | SUCCESSIVE APPROXIMATION AD CONVERTER AND MOBILE WIRELESS DEVICE - A controller controls first and second supply switches so that, during a sampling period, a ground voltage is supplied to n first up-capacitors and n second up-capacitors while a power supply voltage is supplied to n first down-capacitors and n second down-capacitors. The controller also controls the first and second supply switches based on the result of comparison by a comparator during each of n bit determination periods so that a first analog voltage at a first sampling node and a second analog voltage at a second sampling node gradually approach each other. | 12-20-2012 |
20130009796 | CLOCK GENERATOR CIRCUIT FOR SUCCESSIVE APPROXIMATIOM ANALOG TO-DIGITAL CONVERTER - A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio. | 01-10-2013 |
20130154699 | REFERENCE FREQUENCY GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE - An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock. | 06-20-2013 |
20130194719 | CAPACITOR ARRAY AND SIGNAL PROCESSOR INCLUDING THE ARRAY - A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part. | 08-01-2013 |
20130285579 | ACTUATOR DRIVER - A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ΔΣ A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ΔΣ A/D converters to feed back the digital signal to the digital filter. | 10-31-2013 |
20140062750 | REFERENCE VOLTAGE STABILIZER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied. | 03-06-2014 |
20140077979 | SUCCESSIVE APPROXIMATION AD CONVERTER - A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC. | 03-20-2014 |
20140285370 | SUCCESSIVE APPROXIMATION AD CONVERTER AND NOISE GENERATOR - In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed. | 09-25-2014 |