Patent application number | Description | Published |
20100072614 | 3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD - A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer. | 03-25-2010 |
20110216573 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter. | 09-08-2011 |
20110309881 | THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor. | 12-22-2011 |
20120235705 | NONVOLATILE CONFIGURATION MEMORY - According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer. | 09-20-2012 |
20130268795 | CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE - According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit. | 10-10-2013 |
20130322161 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential. | 12-05-2013 |
20140104920 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps. | 04-17-2014 |
20140281189 | PROCESSOR SYSTEM HAVING VARIABLE CAPACITY MEMORY - According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2 | 09-18-2014 |
20140297920 | MULTI-CORE PROCESSOR AND CONTROL METHOD - According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer. | 10-02-2014 |
20140379975 | PROCESSOR - According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas. | 12-25-2014 |