Patent application number | Description | Published |
20110107739 | WARM-UP METHOD AND SYSTEM FOR WARMING UP EXHAUST PURIFICATION CATALYST - A warm-up system for warming up an exhaust purification catalyst arranged in an exhaust passage of an engine equipped with a turbocharger. The warm-up system includes an electric motor coupled to a turbine of the turbocharger, and control device that operates the electric motor to apply counter torque to the turbine when the exhaust purification catalyst needs to be warmed up. | 05-12-2011 |
20110146274 | METHOD AND SYSTEM FOR REGENERATING PARTICULATE FILTER - A particulate filter regeneration system regenerates a particulate filter provided in an exhaust line of an engine equipped with a turbocharger by burning matter trapped on the particulate filter by raising the temperature of exhaust gas at times that the particulate filter requires regeneration. The system has an electric motor functioning as an intake quantity regeneration portion capable of increasing the flow rate of compressed air without depending on the flow rate of exhaust gas flowing across a turbine of the turbocharger, a bypass line connecting an engine intake line upstream of the engine to a section of the exhaust line upstream of the particulate filter, a flow rate regulation valve regulating the flow rate in the bypass line, and a control portion controlling the electric motor and the flow rate regulator. | 06-23-2011 |
20140013742 | POWER-ASSISTED SUPERCHARGER AND METHOD FOR CONTROLLING SAME - The power-assisted supercharger ( | 01-16-2014 |
20140301831 | TURBOCHARGER SYSTEM AND CONTROL METHOD FOR THE SAME - A turbocharger system of an embodiment includes: a wastegate valve; an electrically-operated actuator configured to adjust a valve lift of the wastegate valve; a temperature acquisition unit configured to acquire a target temperature which is a temperature of the turbocharger body or a temperature correlating with the temperature of the turbocharger body; and an actuator controller configured to control the electrically-operated actuator on the basis of the target temperature. The temperature acquisition unit acquires the target temperature, and the actuator controller controls the electrically-operated actuator on the basis of the target temperature. | 10-09-2014 |
Patent application number | Description | Published |
20080270868 | DECODING APPARATUS - In the present application, there is provided a decoding apparatus for decoding low density parity check codes, including: a plurality of storage sections configured to store logarithmic likelihood ratios or logarithmic posteriori probability ratios for one codeword into addresses thereof which are independent of each other thereamong; and a readout section configured to simultaneously read out, from among the logarithmic likelihood ratios or logarithmic posteriori probability ratios for the one codeword stored in the storage sections, a plurality of ones of the logarithmic likelihood ratios or logarithmic posteriori probability ratios which correspond to non-zero value elements in a predetermined one row of the check matrix used in a coding process of the low density parity check codes. | 10-30-2008 |
20080320370 | CRC generator polynomial select method, CRC coding method and CRC coding circuit - Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding processing and/or CRC processing of inspecting a CRC processing result, the CRC generator polynomial select method may include a first process of finding largest minimum Hamming distances Max.d | 12-25-2008 |
20100031124 | Transmission apparatus and method, reception apparatus and method, and program - A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing. | 02-04-2010 |
20100229076 | Decoding Apparatus and Decoding Method - Disclosed herein is a decoding apparatus including: with N and x each being a positive integer and k being a positive integer being equal to or greater than 1, a shift register of k stages configured to accumulate path select information for k inputs that is information about a survivor path of xN bits made up of radix-2 | 09-09-2010 |
20110029838 | Device and Method for Transmission, Device and Method for Reception, and Program - The present invention relates to a device and a method for transmission, a device and a method for reception, and a program that make it possible to obtain an undetected error probability characteristic close to a limit value in a system using a CRC for a plurality of pieces of data having different code lengths. A generator polynomial for header data which generator polynomial is used when a CRC coding process is performed on header data and a generator polynomial for sub-header data which generator polynomial is used when the CRC coding process is performed on sub-header data are set in a transmitting device | 02-03-2011 |
Patent application number | Description | Published |
20100051939 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An interfacial reaction suppressing layer | 03-04-2010 |
20100283083 | Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor - Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region. | 11-11-2010 |
20110261849 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THEREOF - A semiconductor light emitting element comprising: a buffer layer that is grown by using a growth substrate including ZnO, the buffer layer being made by using an AlGaInN-based material including In and being configured so that the growth surface thereof has a nitrogen polar plane; and an active layer that is formed on the buffer layer, the active layer being made by using an AlGaInN-based material including In and being configured so that the growth surface thereof has a group-III polar plane. | 10-27-2011 |
20140374771 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm. | 12-25-2014 |
20150221725 | SEMICONDUCTOR MULTI-LAYER SUBSTRATE AND SEMICONDUCTOR ELEMENT - A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer. | 08-06-2015 |
Patent application number | Description | Published |
20090052238 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more. | 02-26-2009 |
20100220531 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 09-02-2010 |
20110246860 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 10-06-2011 |
20120179953 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 07-12-2012 |
20140203345 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device ( | 07-24-2014 |