Patent application number | Description | Published |
20120097234 | Using Diffusion Barrier Layer for CuZnSn(S,Se) Thin Film Solar Cell - Techniques for fabricating thin film solar cells, such as CuZnSn(S,Se) (CZTSSe) solar cells are provided. In one aspect, a method of fabricating a solar cell is provided that includes the following steps. A substrate is provided. The substrate is coated with a molybdenum (Mo) layer. A stress-relief layer is deposited on the Mo layer. The stress-relief layer is coated with a diffusion barrier. Absorber layer constituent components are deposited on the diffusion barrier, wherein the constituent components comprise one or more of sulfur (S) and selenium (Se). The constituent components are annealed to form an absorber layer, wherein the stress-relief layer relieves thermal stress imposed on the absorber layer, and wherein the diffusion barrier blocks diffusion of the one or more of S and Se into the Mo layer. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20120100663 | Fabrication of CuZnSn(S,Se) Thin Film Solar Cell with Valve Controlled S and Se - Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 04-26-2012 |
20140034118 | THIN FILM SOLAR CELLS - Embodiments relate to a solar cell apparatus including a molybdenum (Mo) contact layer and an annealed absorber layer including zinc and sulfur directly adjacent to the Mo contact layer. The apparatus has no molybdenum disulfide (MoS | 02-06-2014 |
20140038344 | THIN FILM SOLAR CELLS - Embodiments relate to a method including forming a layer of copper zinc tin sulfide (CZTS) on a first layer of molybdenum (Mo) and annealing the CZTS layer and the first Mo layer to form a layer of molybdenum disulfide (MoS | 02-06-2014 |
20140144497 | ATOMIC LAYER DEPOSITION FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer. | 05-29-2014 |
20140147958 | ATOMIC LAYER DEPOSITION FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer. | 05-29-2014 |
20140284547 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 09-25-2014 |
20140284616 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 09-25-2014 |
20140305499 | PROTECTIVE INSULATING LAYER AND CHEMICAL MECHANICAL POLISHING FOR POLYCRYSTALLINE THIN FILM SOLAR CELLS - A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer. | 10-16-2014 |
20140306306 | PROTECTIVE INSULATING LAYER AND CHEMICAL MECHANICAL POLISHING FOR POLYCRYSTALLINE THIN FILM SOLAR CELLS - A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer. | 10-16-2014 |
Patent application number | Description | Published |
20080297547 | FLUID EJECTOR INCLUDING A DROP SIZE SYMBOL, A METHOD OF DISPOSING A DROP SIZE SYMBOL IN A FLUID EJECTOR, AND AN IMAGE FORMING DEVICE INCLUDING A MARKING FLUID EJECTOR WITH A DROP SIZE SYMBOL - A fluid ejector includes a drop size symbol that is based on the fluid ejector's drop size relative to one or more fixed drop sizes. The drop size symbol is formed by comparing the fluid ejector's drop size to the one or more fixed drop sizes. An image forming device includes a marking fluid ejector that includes a drop size symbol based on the marking fluid ejector's drop size relative to one or more fixed drop sizes. The image forming device forms an image based on the drop size symbol by determining the drop size symbol and then either selecting a marking fluid look-up table based on the drop size symbol, or forming an image correction factor based on the drop size symbol. | 12-04-2008 |
20080303850 | FLUID EJECTOR INCLUDING A DROP SIZE SYMBOL, A METHOD OF DISPOSING A DROP SIZE SYMBOL IN A FLUID EJECTOR, AND AN IMAGE FORMING DEVICE INCLUDING A MARKING FLUID EJECTOR WITH A DROP SIZE SYMBOL - A fluid ejector includes a drop size symbol that is based on the fluid ejector's drop size relative to one or more fixed drop sizes. The drop size symbol is formed by comparing the fluid ejector's drop size to the one or more fixed drop sizes. An image forming device includes a marking fluid ejector that includes a drop size symbol based on the marking fluid ejector's drop size relative to one or more fixed drop sizes. The image forming device forms an image based on the drop size symbol by determining the drop size symbol and then either selecting a marking fluid look-up table based on the drop size symbol, or forming an image correction factor based on the drop size symbol. | 12-11-2008 |
20110187777 | Ink Drop Position Correction In The Process Direction Based On Ink Drop Position History - A method compensates for changes in drop velocity of drops emitted by inkjets in a printhead of an ink jet imaging device. The method includes adjusting image data used to generate firing signals for an inkjet ejector in a printhead of an inkjet imaging device with an initial ink drop correction parameter, adjusting a portion of the adjusted image data with another ink drop correction parameter in response to the portion of the adjusted image data corresponding to a predetermined firing pattern mask, generating firing signals for the inkjet ejector from the adjusted image data, and transmitting the generated firing signals to the inkjet ejector in the printhead. | 08-04-2011 |
20110242186 | Test Pattern Effective For Coarse Registration Of Inkjet Printheads And Method Of Analysis Of Image Data Corresponding To The Test Pattern In An Inkjet Printer - A test pattern printed by printheads in an inkjet printer enables image analysis of the test pattern that identifies positions of the printheads and the inkjets operating in the printheads. The test pattern includes a plurality of arrangements of dashes, each arrangement of dashes having a predetermined number of rows and a predetermined number of columns, each dash in a row of dashes in the arrangement of dashes being separated by a first predetermined distance and each dash in a column of dashes in the arrangement of dashes being separated by a second predetermined distance, each dash in a column of an arrangement of dashes being ejected by a single inkjet ejector in a printhead of the inkjet printer, and a plurality of unprinted areas interspersed between the plurality of arrangements of dashes. | 10-06-2011 |
20110279503 | Method And System For Measuring And Compensating For Process Direction Artifacts In An Optical Imaging System In An Inkjet Printer - A printer operating method enables a controller to identify process direction errors in an optical imaging system. The method includes identifying a printhead roll error for each printhead in a plurality of printheads in a printer, moving each printhead by an amount that corrects the printhead roll error for the corresponding printhead, generating a plurality of dashes on media with the plurality of printheads as the media moves past the plurality of printheads, identifying a position for each dash in the process direction from image data of the plurality of dashes on the media, identifying a displacement in the process direction for each optical detector in a linear array of optical detectors used to generated the image data of the plurality of dashes, the displacement being identified with reference to the identified positions for the dashes, and operating the printer to compensate for the identified displacements of the optical detectors. | 11-17-2011 |
20110279505 | Method For Identifying And Verifying Dash Structures As Candidates For Test Patterns And Replacement Patterns In An Inkjet Printer - A method compensates for changes in drop velocity of drops emitted by inkjets in a printhead of an ink jet imaging device. The method includes operating inkjet ejectors in a plurality of printheads to eject ink in a pattern of structured dashes on an image receiving member, the structured dashes corresponding to a predetermined image data pattern, generating image data corresponding to the pattern of structured dashes on the image receiving member, identifying a process direction correction parameter for each ejector in the plurality of printheads with reference to the generated image data, modifying image data to be printed by the plurality of printheads with reference to the process direction correction parameter identified for at least one of the ejectors, and operating the plurality of printheads with reference to the modified image data. | 11-17-2011 |
20130106936 | METHOD AND SYSTEMS FOR CREATING A PRINTER MODEL BASED ON PRINT COLUMNS | 05-02-2013 |
20130236063 | MULTIPLE VIEW TRANSPORTATION IMAGING SYSTEMS - A camera may be positioned to have a direct view of on-coming vehicle traffic from a first perspective. Additionally, a reflective surface, such as a mirror, may be positioned within the viewing area of the same camera to provide the camera with a reflected view of vehicle traffic from a second perspective. The images recorded by the camera may then be received by a computing device. The computing device may separate the images into a direct view region and a reflected view region. After separation, the regions may be analyzed independently and/or combined with other regions, and the analyzed data may be stored. The regions may be analyzed to determine various vehicle characteristics, including, but not limited to, vehicle speed, license plate identification, vehicle occupancy, vehicle count, and vehicle type. | 09-12-2013 |
20140015882 | System and Method for Sub-Pixel Ink Drop Adjustment for Process Direction Registration - A method of operating an inkjet printer reduces ink drop placement errors in a process direction. The method includes generating firing signals for inkjets in a printhead at a first frequency and initiating the generation of the firing signals to a first plurality of inkjets in the printhead at a second frequency, the first frequency being greater than the second frequency. | 01-16-2014 |
20140198146 | System And Method For Process Direction Registration Of Inkjets In A Printer Operating With A High Speed Image Receiving Surface - A method for process direction registration in an inkjet printer includes ejecting ink drops from a first inkjet at less than a maximum operating rate onto an image receiving surface moving in a process direction. The method includes generating image data samples of the image receiving surface including the ink drops. The method further includes identifying a center of the ink drops in the process direction with reference to the image data samples and storing a time offset value in a memory to correct an identified process direction offset between the identified center of the ink drops and another identified center of ink drops that are ejected by another inkjet. | 07-17-2014 |
Patent application number | Description | Published |
20080256383 | METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 10-16-2008 |
20090013207 | PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 01-08-2009 |
20130339762 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 12-19-2013 |
20130339917 | AUTOMATING CURRENT-AWARE INTEGRATED CIRCUIT AND PACKAGE DESIGN AND OPTIMIZATION - A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 12-19-2013 |
20140082574 | Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140082580 | CURRENT-AWARE FLOORPLANNING TO OVERCOME CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140195996 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 07-10-2014 |
Patent application number | Description | Published |
20080295981 | SINGLE VESSEL REACTOR SYSTEM FOR HYDROLYSIS AND DIGESTION OF WOOD CHIPS WITH CHEMICAL ENHANCED WASH METHOD - A reaction vessel including: a material input receiving cellulosic material and a material discharge for the cellulosic material, wherein the cellulosic material flows through the reaction vessel from the material input to the material discharge; a hydrolysate and liquid extraction screen; a hydrolysis zone between the material input and the hydrolysate and liquid extraction screen; a wash zone between the hydrolysate and liquid extraction screen and a wash liquid extraction screen; a wash liquid inlet port for introducing a wash liquid into the wash zone, wherein at least a portion of the wash liquid entering the wash liquid inlet port flows through the wash zone and is extracted by the hydrolysate and liquid extraction screen; a cooking zone between the wash zone and the material discharge and a cooking liquor extraction screen at or below the cooking zone and above the material discharge. | 12-04-2008 |
20080302492 | TWO VESSEL REACTOR SYSTEM AND METHOD FOR HYDROLYSIS AND DIGESTION OF WOOD CHIPS WITH CHEMICAL ENHANCED WASH METHOD - A reactor vessel system including: a first reactor vessel having a hydrolysate and liquid extraction screen, a first region above the extraction screen that is maintained at conditions promoting a hydrolysis reaction in the cellulosic material, a second region below the extraction screen in which the hydrolysis is substantially suppressed and a wash liquid inlet below the extraction screen providing wash liquid at a temperature below a hydrolysis temperature; a transport pipe having an inlet coupled to the first reactor vessel and an outlet coupled to a second reactor vessel, and the second reactor vessel includes a liquid discharge that extracts a portion of liquid from the second reactor vessel and directs the portion of liquid to the first reactor vessel or to the transport pipe. | 12-11-2008 |
20090032208 | PROCESSES AND SYSTEMS FOR THE BLEACHING OF LIGNOCELLULOSIC PULPS FOLLOWING COOKING WITH SODA AND ANTHRAQUINONE - Process for bleaching of pulps following cooking of the lignocellulosic material with soda and anthraquinone. The process may produce a whiteness on par with the bleaching of kraft pulp when using a similar bleaching sequence. In some instances, the bleaching sequence may be O-A-Do-Eop-D, O-A-ZDo-Eop-D, A-Do, or A-ZDO. | 02-05-2009 |
20090308383 | APPARATUS AND METHOD FOR HYDROLYSIS OF CELLULOSIC MATERIAL IN A MULTI-STEP PROCESS TO PRODUCE C5 AND C6 SUGARS USING A SINGLE VESSEL - A system and method for extracting C | 12-17-2009 |
20090318679 | APPARATUS AND METHOD FOR HYDROLYSIS OF CELLULOSIC MATERIAL IN A TWO-STEP PROCESS - A system and method for extracting pentose from a slurry of cellulosic material comprising cellulose, water, and optionally acid in a two-stage process. | 12-24-2009 |
20100116267 | APPARATUS AND METHOD FOR TREATING, PRESSING AND WASHING BIOMASS - A biomass cooking device including: a treatment vessel having an biomass inlet adapted to receive biomass material to a processing chamber of the vessel, a biomass outlet adapted to discharge from the processing chamber the biomass material processed in the vessel, an extraction region of the vessel and a liquids outlet to the extraction region to discharge dissolved hemi-cellulosic material extracted from the biomass material in the processing chamber; a piston press in the cooking vessel defining a moveable wall of the processing chamber, wherein the piston press moves to reduce the processing chamber and thereby compress the biomass material; and a screen plate in the vessel forming a barrier between the processing chamber and an extraction region of the vessel, the screen plate having apertures to pass the dissolved hemi-cellulosic material through the screen plate from the processing chamber to the extraction region. | 05-13-2010 |
20100263813 | GREEN LIQUOR PRETREATMENT OF LIGNOCELLULOSIC MATERIAL - A continuous process for producing a chemical grade pulp, the process comprising the steps of: (a) steaming lignocellulosic material for a first period of time between 1 and 60 minutes; (b) after steaming, impregnating the steamed lignocellulosic material in an impregnation vessel with green liquor for a second period of time up to 5 minutes and at a temperature between 110° C. and 150° C.; and (c) after impregnation, continuously cooking the lignocellulosic material in a digester to produce a chemical grade pulp. | 10-21-2010 |
20110290238 | APPARATUS AND METHOD FOR HYDROLYSIS OF CELLULOSIC MATERIAL IN A TWO-STEP PROCESS - A system and method for extracting pentose from a slurry of cellulosic material comprising cellulose, water, and optionally acid in a two-stage process. | 12-01-2011 |
20110303217 | APPARATUS AND METHOD FOR HYDROLYSIS OF CELLULOSIC MATERIAL IN A MULTI-STEP PROCESS TO PRODUCE C5 AND C6 SUGARS USING A SINGLE VESSEL - A system and method for extracting C | 12-15-2011 |