Patent application number | Description | Published |
20100029047 | METHOD OF FABRICATING PRINTED CIRCUIT BOARD HAVING SEMICONDUCTOR COMPONENTS EMBEDDED THEREIN - A method for fabricating a printed circuit board having semiconductor components embedded therein is provided. A carrier board having at least a predetermined hole area is provided. A plurality of through holes are formed in the surround of the predetermined hole area on the carrier board. A rectangular cavity is formed by punching to remove the predetermined hole area, and a plurality of through holes are formed around the rectangular cavity The through holes facilitate receipt of the semiconductor chip and filling of a fixing material in the rectangular cavity, to avoid displacement of the semiconductor chip in subsequent fabricating steps that would otherwise cause a drawback, that is, a wiring to be formed later is improperly electrically connected to the semiconductor chip. | 02-04-2010 |
20100032827 | PACKAGE STRUCTURE - Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance. | 02-11-2010 |
20100052148 | PACKAGE STRUCTURE AND PACKAGE SUBSTRATE - Provided are a package structure and a package substrate, including: a substrate body having a plurality of matrix-arranged electrical contact pads formed on at least one surface thereof, wherein a solder mask layer is formed on said surface and has a plurality of openings for exposing the electrical contact pads, respectively; a first electroless-plated layer disposed on the electrical contact pads, on the walls of the openings and at the peripheries of the openings; and a second electroless-plated layer disposed on the first electroless-plated layer, the first and second electroless-plated layers constituting a recessed electrical connection structure. By forming the even electroless-plated layers on the electrical contact pads. The invention overcomes drawbacks of the prior art, namely breakage of interfaces between solder bumps and electrical contact pads and even damage of the package structure otherwise caused by excessive differences in stress between the solder bumps. | 03-04-2010 |
20100108345 | LID FOR MICRO-ELECTRO-MECHANICAL DEVICE AND METHOD FOR FABRICATING THE SAME - A lid for a micro-electro-mechanical device and a method for fabricating the same are provided. The lid includes a board with opposite first and second surfaces and a first conductor layer. The first surface has a first metal layer thereon. The first metal layer and the board have a recess formed therein. The recess has a bottom surface and a side surface adjacent thereto. The first conductor layer is formed on the first metal layer and the bottom and side surfaces of the recess. The shielding effect of the side surface of the board is enhanced because of the recess integral to the board, the homogeneous bottom and side surfaces of the recess, and the first conductor layer covering the first metal layer, the bottom and side surfaces of the recess. Hence, the shielding effect upon the micro-electro-mechanical device is enhanced. | 05-06-2010 |
20110042128 | CORELESS PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided. | 02-24-2011 |
20110097850 | METHOD OF FABRICATING A PACKAGING STRUCTURE - A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result. | 04-28-2011 |
20110097851 | METHOD OF FABRICATING A PACKAGE STRUCTURE - A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced. | 04-28-2011 |
20110154664 | STRUCTURE OF CIRCUIT BOARD AND METHOD FOR FABRICATING THE SAME - A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices. | 06-30-2011 |
20120013002 | PACKAGE STRUCTURE - Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance. | 01-19-2012 |
20120037404 | PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN AND METHOD OF FABRICATING THE SAME - A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height. | 02-16-2012 |
20120037411 | PACKAGING SUBSTRATE HAVING EMBEDDED PASSIVE COMPONENT AND FABRICATION METHOD THEREOF - A packaging substrate includes: a core board with at least a cavity; a dielectric layer unit having upper and lower surfaces and encapsulating the core board and filling the cavity; a plurality of positioning pads embedded in the lower surface of the dielectric layer unit; at least a passive component having upper and lower surfaces with electrode pads disposed thereon and embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position corresponding to the positioning pads; first and second wiring layers disposed on the upper and lower surfaces of the dielectric layer unit and electrically connected to the electrode pads of the upper and lower surfaces of the passive component through conductive vias, respectively. By embedding the passive component in the core board and the dielectric layer unit, the invention effectively reduces the height of the overall structure. | 02-16-2012 |
20120104598 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 05-03-2012 |
20120181688 | PACKAGING SUBSTRATE WITH CONDUCTIVE STRUCTURE - A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure. | 07-19-2012 |
20120193789 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate. | 08-02-2012 |
20130230947 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented. | 09-05-2013 |
20130318785 | METHOD FOR MANUFACTURING IC SUBSTRATE - A method for manufacturing an IC substrate includes following steps: providing a roll of double-sided flexible copper clad laminate; converting the roll of double sided flexible copper clad laminate into a roll of double sided flexible wiring board in a roll to roll manner; cutting the roll of double-sided flexible wiring board into a plurality of separate sheets of double sided flexible wiring board; forming first and second rigid insulating layers on the first and second wiring layers of each sheet of double sided flexible wiring board; forming third and fourth wiring layers on the first and second rigid insulating layers, and electrically connecting the first and third wiring layers, and electrically connecting the fourth and second wiring layers, thereby obtaining a sheet of substrate having a plurality of IC substrate units; and cutting the sheet of substrate into separate IC substrate units. | 12-05-2013 |
20130341073 | PACKAGING SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A packaging substrate includes an insulating layer, a wiring layer and a solder mask. The insulating layer and the solder mask being arranged on two opposite sides of the wiring layer. The insulating layer defines a via hole. The wiring layer covers the via hole. The wiring layer includes a pad area. Two sides of the pad area are respectively exposed outside from the solder mask and in the via hole. | 12-26-2013 |
20140000950 | MULTI-LAYER CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME | 01-02-2014 |
20140035138 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 02-06-2014 |
20140036465 | PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING BODY HAVING SAME - A packaging substrate includes a copper foil substrate, a sputtering copper layer, a dielectric layer, a plurality of electrically conductive connection points, and an electrically conductive pattern layer. The sputtering copper layer is formed on the copper foil substrate. The electrically conductive connection points are formed on a surface of the sputtering copper layer, which is away from the copper foil substrate. The dielectric layer is sandwiched between the electrically conductive pattern layer and the sputtering copper layer. A plurality of first blind via are formed in the first dielectric layer. The electrically conductive pattern layer includes a plurality of electrically conductive traces and a plurality of connection pads. Each electrically conductive connection point is electrically connected to the electrically conductive trace by the first blind via. | 02-06-2014 |
20140061903 | PACKAGE ON PACKAGE STRUCTRUE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a package on package structure includes the steps of: providing a connection substrate comprising a main body and electrically conductive posts, the main body comprising a first surface and an opposite second surface, each electrically conductive post passing through the first and second surfaces, and each end of the two ends of the electrically conductive post protruding from the main body; arranging a first package device on a side of the first surface of the connection substrate, arranging a package adhesive on a side of the second surface of the connection substrate, thereby obtaining a semi-finished package on package structure; and arranging a second package device on a side of the package adhesive furthest from the first package device, thereby obtaining a package on package structure. | 03-06-2014 |
20140078706 | PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING BODY HAVING SAME - A packaging substrate includes a supporting sheet, a copper foil, a number of connecting pads, a number of solder balls, a resin layer, a wiring layer and a solder mask layer. The copper foil is attached on a surface of the supporting sheet through an adhesive sheet. The connecting pads are formed on the copper foil. The solder balls are formed on the connecting pads. The resin layer infills the gaps between the solder balls. The wiring layer is formed on the resin layer and the solder balls. Terminal portions of the solder balls facing away from the connecting pads are electrically connected to the wiring layer. The solder mask layer is formed on the wiring layer. The solder mask layer defines a number of openings exposing portions of the wiring layer. The portions of the wiring layer exposed through the openings serve as contact pads. | 03-20-2014 |
20140085833 | CHIP PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING STRUCTURE HAVING SAME - A chip packaging substrate includes a dielectric layer, a first inner wiring layer embedded in the dielectric layer, an outer wiring layer, and many conductive connection points. The outer wiring layer is formed at one side of the dielectric layer, and is electrically connected to the first inner wiring layer through many first conductive vias in the dielectric layer. The conductive connection points are formed at the other side of the dielectric layer, and are electrically connected to the first inner wiring layer through many second conductive vias in the dielectric layer. | 03-27-2014 |
20140118951 | INTERPOSER AND PACKAGE ON PACKAGE STRUCTURE - A heat-dissipating interposer includes an insulating base, a plurality of conductive pillars and a thermal conducting frame. The insulating base includes a first surface and an opposite second surface. The conductive pillars are arranged on the insulating base. The conductive pillars protrude from the second surface. The height of the conductive pillars relative to the second surface is greater than the thickness of the insulating base. The thermal conducting frame is placed on the second surface and receives a heat-generating component. The interposer can be used in a package on package structure. | 05-01-2014 |
20140144675 | MULTI-LAYER PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING SAME - An exemplary multi-layer printed circuit board includes a multi-layer substrate with a recess, and a first high density wiring substrate received in the recess. The multi-layer substrate includes a base layer, a first wiring layer arranged on the base layer, first insulating layers, and third wiring layers. The first insulating layers and the third wiring layers are alternately arranged on the first wiring layer, such that there is one first insulating layer sandwiched between each two adjacent wiring layers of the first wiring layer and the third wiring layers. The first high density wiring substrate includes first high density wiring layers and third insulating layers, which are alternately arranged on each other. An outmost first high density wiring layer is exposed outside to define third electrical contact pads corresponding to the first electrical contact pads. | 05-29-2014 |
20140182892 | PRINTED CIRCUIT BOARD WITH EMBEDDED COMPONENT AND METHOD FOR MANUFACTRUING SAME - A printed circuit board with an embedded component includes a double-sided wiring board, an electronic component, and many conductive pastes. The wiring board includes a first wiring layer, a base layer, a first insulating layer, and a second wiring layer. The base layer has an opening exposing a portion of the second surface of the first insulating layer to the outside. The second wiring layer includes electrical contact pads. The conductive blind vias are formed in the first insulating layer. Each electrical contact pad is electrically connected to an end of the corresponding conductive blind via. The other ends of the conductive blind vias are adjacent to the first surface. A filling through hole is formed in the double-sided wiring board. The conductive pastes are respectively electrically connected to the conductive blind vias. The electronic component is adhered to and electrically connected to the conductive paste. | 07-03-2014 |
20140185257 | PRINTED CIRCUIT BOARD WITH EMBEDDED COMPONENT AND METHOD FOR MANUFACTURING SAME - A printed circuit board with embedded component includes a double-sided printed circuit board, an electronic component, a plurality of conductive paste blocks, an insulating layer and a wiring layer near the first wiring layer, an insulating layer and a wiring layer near the second wiring layer. The double-sided printed circuit board comprising a first wiring layer, a base, and a second wiring layer. The first wiring layer and the second wiring layer are arranged on opposite sides of the base. The second wiring layer includes a plurality of electrical contact pads. The base defines a number of conductive vias. Each electrical contact pad is aligned with and electrically connected to one corresponding conductive via. The conductive paste blocks are electrically connecting to the conductive vias. The electronic component is electrically connected to the conductive paste blocks. The two insulating layers cover the electronic component and the second wiring layer. | 07-03-2014 |
20140300009 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - A package structure includes a flexible-rigid PCB and a chip. The flexible PCB includes a flexible PCB, a glue piece and an outer trace layer. The flexible PCB includes two bending portions and a fixing portion connected between the two bending portions, and includes an insulating layer and an inner trace layer formed on the insulating layer. The glue piece is adhered to the fixing portion. The outer trace layer is adhered to the glue piece and includes conductive pads. The fixing portion, the glue piece and the outer trace layer form a rigid portion, the bending portions form flexible portions. The chip is packaged on the rigid portion and includes electrode pads electrically connected to the conductive pads. | 10-09-2014 |
20140345125 | METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN - A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height. | 11-27-2014 |
20140345126 | METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN - A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height. | 11-27-2014 |
20140345930 | PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN - A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height. | 11-27-2014 |
20140374894 | PACKAGE ON PACKAGE STRUCTRUE AND METHOD FOR MANUFACTURING SAME - A package on package structure includes a connection substrate having a main body and electrically conductive posts, the main body includes a first surface and an opposite second surface, and each electrically conductive post passes through the first and second surfaces, and each end of the two ends of the electrically conductive post protrudes from the main body; a first package device arranged on a side of the first surface of the connection substrate; a package adhesive arranged on a side of the second surface of the connection substrate; and a second package device arranged on a side of the package adhesive furthest away from the first package device. | 12-25-2014 |