Patent application number | Description | Published |
20080230878 | Leadframe based flip chip semiconductor package and lead frame thereof - A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products. | 09-25-2008 |
20120001274 | WAFER LEVEL PACKAGE HAVING A PRESSURE SENSOR AND FABRICATION METHOD THEREOF - A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path. | 01-05-2012 |
20120018870 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result. | 01-26-2012 |
20120056279 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element includes: a packaging substrate having first and second wiring layers on two surfaces thereof and a chip embedded therein; a first dielectric layer disposed on the packaging substrate and the chip; a third wiring layer disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and the third wiring layer and having a recessed portion; a lid disposed in the recessed portion and on the top surface of the second dielectric layer around the periphery of the recessed portion, wherein the portion of the lid on the top surface of the second dielectric layer is formed into a lid frame on which an adhering material is disposed to allow a substrate having an MEMS element to be attached to the packaging substrate with the MEMS element corresponding in position to the recessed portion, thereby providing a package structure of reduced size and costs with better electrical properties. | 03-08-2012 |
20120086117 | PACKAGE WITH EMBEDDED CHIP AND METHOD OF FABRICATING THE SAME - A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified. | 04-12-2012 |
20120104517 | PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT AND MANUFACTURING METHOD THEREOF - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 05-03-2012 |
20120129315 | Method for fabricating semiconductor package - A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board. | 05-24-2012 |
20120286425 | PACKAGE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization. | 11-15-2012 |
20120292722 | PACKAGE STRUCTURE HAVING MEMS ELEMENTS AND FABRICATION METHOD THEREOF - A package structure having MEMS elements includes: a wafer having MEMS elements, electrical contacts and second alignment keys; a plate disposed over the MEMS elements and packaged airtight; transparent bodies disposed over the second alignment keys via an adhesive; an encapsulant disposed on the wafer to encapsulate the plate, the electrical contacts and the transparent bodies; bonding wires embedded in the encapsulant and each having one end connecting a corresponding one of the electrical contacts and the other end exposed from a top surface of the encapsulant; and metal traces disposed on the encapsulant and electrically connected to the electrical contacts via the bonding wires. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce fabrication costs. Further, the present invention accomplishes wiring processes by using a common alignment device to thereby reduce equipment costs. | 11-22-2012 |
20120313243 | CHIP-SCALE PACKAGE - A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer. | 12-13-2012 |
20130020709 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The semiconductor package includes a carrier having a plurality bonding pads disposed on a surface thereof, a packaging layer formed on the surface of the carrier and having a plurality of openings corresponding to the bonding pads, a conductive material filled in the openings and electrically connected to the bonding pads, and an electronic component installed on the packaging layer and having a plurality of conductive pillars correspondingly received in the openings and electrically connected to the conductive material. The formation of the openings in the packaging layer can control the position and size of the conductive material to enable the overall height of the conductive structure to be level and to keep the electronic component from tilting. | 01-24-2013 |
20130187285 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 07-25-2013 |
20130228915 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs. | 09-05-2013 |
20130249589 | INTERPOSER AND ELECTRICAL TESTING METHOD THEREOF - An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer. | 09-26-2013 |
20130256875 | SEMICONDUCTOR PACKAGE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 10-03-2013 |
20130341774 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield. | 12-26-2013 |
20140015125 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements. | 01-16-2014 |
20140021629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy. | 01-23-2014 |
20140080242 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 03-20-2014 |
20140134797 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips. | 05-15-2014 |
20140154842 | CARRIER, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided. | 06-05-2014 |
20140252603 | SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE VIAS - A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield. | 09-11-2014 |
20140342507 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 11-20-2014 |
20150035163 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced. | 02-05-2015 |
20150035164 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced. | 02-05-2015 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 02-12-2015 |
20150069628 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided. | 03-12-2015 |