Patent application number | Description | Published |
20090146299 | SEMICONDUCTOR PACKAGE AND METHOD THEREOF - A ball grid array (BGA) structure package includes: a circuit board including a top surface and a bottom surface, and the top surface includes a patterned metal point disposed thereon and the bottom surface includes a metal point corresponding to the patterned conductive point; a semiconductor die includes an active surface, and the active surface includes a plurality of pads disposed thereon and the pads is electrically connected to the patterned metal point; a package body used to encapsulate the semiconductor die and the top surface of the circuit board; and a plurality of conductive elements electrically connected to the bottom surface of the circuit board. | 06-11-2009 |
20140183713 | DIE PACKAGE STRUCTURE - The die package structure includes a die, and the pads on one side of the active surface of the die. The connecting terminal is disposed on one side of the packaged substrate region and is passed through the packaged substrate region. The external connecting terminal is disposed on another side adjacent to the connecting terminal. The back surface of the packaged substrate region is fixed on the die by the adhesive layer, and the pad of the die is to be exposed. A conductive wire electrically connected the connecting terminal with the pads on the die. A packaged body encapsulated the packaged substrate region, the active surface of the die and the conductive wire, and the external connecting terminal is to be exposed. A conductive component is electrically connected with the connecting terminal and being exposed on the packaged body. | 07-03-2014 |
20140183714 | DIE PACKAGE STRUCTURE - A die packaged structure is provided, which includes a die having the pad disposed on one side of the active surface. A packaged substrate having a front surface and a back surface, and the connecting terminal disposed on one side of the packaged substrate region, and passed through the packaged substrate region. An opening is disposed between the connecting terminal and one side of the packaged substrate region. Then, the back surface of the packaged substrate is fixed on die by an adhesive layer, such that the pad is exposed on the opening of the packaged substrate region. A conductive wire is electrically connected the pad with the connecting terminal, and a packaged body is encapsulated the packaged substrate region, the die and the conductive wire, and the external connecting terminal is exposed on the packaged substrate region. A conductive component is arranged on the external connecting terminal. | 07-03-2014 |
20140197524 | DIE PACKAGE STRUCTURE - A die packaged structure includes a pad on the central region of the die. A packaged substrate with an opening disposed in the central region, and a connecting terminal is passed through the packaged substrate and disposed around the opening. An external connecting terminal is disposed on the four sides of the packaged substrate. A first metal wire is electrically connected the connecting terminal with the external connecting terminal, and the back of the packaged substrate is fixed on the die, such that the pad is exposed on the opening. A second metal wire is electrically connected the pad with the connecting terminal. A packaged body is encapsulated the packaged substrate, the die and the second metal wire, and the external connecting terminal is exposed. A conductive component is electrically connected with the external connecting terminal and is arranged on the four sides of the die packaged structure. | 07-17-2014 |
20150061152 | PACKAGE MODULE WITH OFFSET STACK DEVICE - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections is disposed on the surface substrate that is opposite to the carrier. A plurality of outer connections on another surface of the substrate is electrically connected with the plurality of electric connections. The group of the stacked device is electrically connected with the carrier by the connecting the plurality of metal connections and the pads. The plurality of metal connections is extended to the bottom of the carrier to form another metal connection to electrically connect with the electric connection on the substrate. | 03-05-2015 |
20150108662 | PACKAGE MODULE WITH OFFSET STACK DEVICE - A package module with offset stacked device is provided which includes a group of stacked device, a carrier and a substrate. The group of stacked device is offset stacked to dispose in the carrier and the substrate is disposed on the bottom of the carrier. A plurality of electric connections is disposed on the surface substrate that is opposite to the carrier. A plurality of outer connections on another surface of the substrate is electrically connected with the plurality of electric connections. The group of the stacked device is electrically connected with the carrier by the connecting the plurality of metal connections and the pads. The plurality of metal connections is extended to the bottom of the carrier to form another metal connection to electrically connect with the electric connection on the substrate. | 04-23-2015 |
20150115476 | Module with Stacked Package Components - A module with stack package components includes: at least a package component in a loader. Moreover, each package components includes at least a chip. Package components stacks in the loader. The package components connect with the loader by metal connecters and wire. These package components are placed to make the loader be the module with stack package components. The module connects with some sockets by other metal connecters. | 04-30-2015 |
Patent application number | Description | Published |
20110056868 | Packing Structure - The present invention provides a packing structure comprising a housing and a cushion portion. The housing includes a bottom plate and a sidewall while the cushion portion is disposed on the bottom plate of the housing. A groove and a jaw portion are formed on an end portion of the cushion portion. The jaw portion is located on a side of the groove facing the sidewall and extends away from the bottom plate. A first tongue plate is formed on the sidewall of the housing and bends inward. A free end of the first tongue plate enters the groove through an opening of the groove, wherein a backside of the jaw portion interferes with the first tongue plate to restrict the first tongue plate from leaving the groove. When the cushion portion is under external forces and moves away from the bottom plate, the first tongue plate will support a bottom inner surface within the groove to restrict a displacement of the cushion portion away from the bottom plate. | 03-10-2011 |
20130319905 | CARRIER TRAY AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a carrier tray includes softening and disposing a plastic film on a first mold, wherein the first mold includes a top surface and a first lateral surface, the top surface includes a recession and a first edge, the first lateral surface is connected to the top surface and extends from the first edge, and the first lateral surface and the top surface form a first included angle; attaching the plastic film to the top surface and the first lateral surface; disposing a restorer on an outer side of the first mold; separating the first mold from the plastic film, wherein the plastic film is pushed by the first lateral surface such that the restorer is moved from an initial position to a final position; and pushing the plastic film from the final position to the initial position by the restorer; and cooling the plastic film. | 12-05-2013 |
20150158664 | CARRIER TRAY - A carrier tray includes a top plate and a first sidewall. The top plate includes a first side edge and a containing room. The first sidewall is connected to the top plate and is extended from the first side edge. The containing room and the first sidewall are disposed on the same side of the top plate. The first sidewall and the top plate form a first included angle of between 73 and 78 degrees therebetween. | 06-11-2015 |
Patent application number | Description | Published |
20130137266 | MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES - Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed. | 05-30-2013 |
20130140666 | SELF-ALIGNED IMPLANTS TO REDUCE CROSS-TALK OF IMAGING SENSORS - A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region. | 06-06-2013 |
20130168794 | Seamless Multi-Poly Structure and Methods of Making Same - A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability. | 07-04-2013 |
20130175660 | Dummy Gate Structure for Semiconductor Devices - A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer. | 07-11-2013 |
20130207163 | Semiconductor Devices and Manufacturing Methods Thereof - Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less. | 08-15-2013 |
20130323876 | IMAGE DEVICE AND METHODS OF FORMING THE SAME - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 12-05-2013 |
20130323917 | SELF-ALIGNED PATTERNING FOR DEEP IMPLANTATION IN A SEMICONDUCTOR STRUCTURE - Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type. | 12-05-2013 |
20140264502 | SELF-ALIGNED IMPLANTS TO REDUCE CROSS-TALK OF IMAGING SENSORS - A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region. | 09-18-2014 |
20150255503 | Image Device and Methods of Forming the Same - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 09-10-2015 |
20160005814 | Dummy Gate Structure for Semiconductor Devices - A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer. | 01-07-2016 |
20160027839 | METHOD OF PREPARING SELF-ALIGNED ISOLATION REGIONS BETWEEN SENSOR ELEMENTS - A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements, wherein a top portion of the deep doped region is below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with the top portion of the deep doped region. | 01-28-2016 |
Patent application number | Description | Published |
20140180219 | NEEDLELESS CONNECTOR - A needleless connector includes a hollow connector, a spring, and a switch assembly. The inner perimeter of the hollow connector forms a first annular wall and a second annular wall. The spring is disposed in the hollow connector. The switch assembly has a stop member and a guide tube connected to the stop member, the stop member being pressed between the annular block and the spring, the guide tube being disposed in the hollow connector, the external perimeter of the stop member forming a first annular portion against the first annular wall and a second annular portion against the second annular wall, a groove being disposed between the first annular portion and the second annular portion of the stop member, the groove being connected to the guide tube. Thus, the integral structure stability and good closing performance are achieved such that the outside air cannot leak into the connector structure. | 06-26-2014 |
20140180258 | NEEDLE-FREE CONNECTOR - A needle-free connector includes a hollow connector, an elastic block, and a switch assembly. The inner perimeter of the hollow connector forms a first annular wall and a second annular wall. The elastic block is disposed in the hollow connector. The switch assembly has a stop member and a guide tube connected to the stop member, the stop member being pressed between the annular block and the elastic block, the guide tube being disposed in the hollow connector, the external perimeter of the stop member forming a first annular portion against the first annular wall and a second annular portion against the second annular wall, a groove being disposed between the first annular portion and the second annular portion of the stop member, the groove being connected to the guide tube. Thus, the structure stability and closing performance are achieved such that the outside air cannot leak into the connector. | 06-26-2014 |
Patent application number | Description | Published |
20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
20160043186 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess. | 02-11-2016 |
20160049321 | SEMICONDUCTOR BAKING APPARATUS AND OPERATION METHOD THEREOF - A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles. | 02-18-2016 |
Patent application number | Description | Published |
20100088070 | FILE-CONVERTING METHOD AND APPLICATION THEREOF - A file-converting method is disclosed. The file-converting method includes the following steps. Obtain an architecture file from Mechanical Computer-aided Design (MCAD) software. Analyze the architecture file to obtain at least an architecture element, which is not compatible with Electrical Computer-aided Design (ECAD) software, according to a converting database. Replace the architecture element in the architecture file with a symbol element, which is compatible with the ECAD software, to generate a layout file. | 04-08-2010 |
20130055173 | GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying. | 02-28-2013 |
20130293899 | APPARATUS FOR CHARGED PARTICLE LITHOGRAPHY SYSTEM - The present disclosure describes an apparatus of leveling a substrate in a charged particle lithography system. In an example, the apparatus includes a cantilever-based sensor that includes an optical sensor and a cantilever structure. The optical sensor determines a distance between the optical sensor and a surface of the substrate based on light reflected from the cantilever structure. In an example, a first distance is between the cantilever structure and optical sensor, a second distance is a height of the cantilever structure, and a third distance is between the optical sensor and the surface of the substrate. The optical sensor determines the first distance based on the light reflected from the cantilever structure, such that the third distance is determined from the first distance and the second distance. | 11-07-2013 |
20130320243 | EFFICIENT SCAN FOR E-BEAM LITHOGRAPHY - The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning. | 12-05-2013 |
20130323648 | SMART SUBFIELD METHOD FOR E-BEAM LITHOGRAPHY - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved. | 12-05-2013 |
20140023972 | Data Process for E-Beam Lithography - The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system. | 01-23-2014 |
20140099582 | Smart Subfield Method For E-Beam Lithographny - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved. | 04-10-2014 |
Patent application number | Description | Published |
20150344551 | COMPOSITIONS AND METHODS FOR TREATMENT AND DETECTION OF CANCERS - Pharmaceutical composition comprising antibodies or antigen binding fragments thereof that bind to SSEA-4 are disclosed herein, as well as methods of use thereof. Methods of use include, without limitation, cancer therapies and diagnostics. The antibodies of the disclosure can bind to certain cancer cell surfaces. Exemplary targets of the antibodies disclosed herein can include carcinomas, such as those in brain, lung, breast, mouse, esophagus, stomach, liver, bile duct, pancreas, colon, kidney, cervix, ovary, and/or prostate cancer. | 12-03-2015 |
20160102151 | COMPOSITIONS AND METHODS FOR TREATMENT AND DETECTION OF CANCERS - Pharmaceutical composition comprising antibodies or antigen binding fragments thereof that bind to globo H, SSEA3, and SSEA-4 are disclosed herein, as well as methods of use thereof. Methods of use include, without limitation, cancer therapies and diagnostics. The antibodies of the disclosure can bind to certain cancer cell surfaces. Exemplary targets of the antibodies disclosed herein can include carcinomas, such as those in brain, skin, bone, lungs, breast, esophagus, stomach, liver, bile duct, pancreas, colon, kidney, cervical, ovarian, and/or prostate cancer. | 04-14-2016 |