Patent application number | Description | Published |
20080217675 | Novel profile of flash memory cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 09-11-2008 |
20080248620 | Gated semiconductor device and method of fabricating same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 10-09-2008 |
20090026432 | METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE - A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process. | 01-29-2009 |
20090029547 | NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION - A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps. | 01-29-2009 |
20110006355 | Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. | 01-13-2011 |
20110165746 | Novel Profile of Flash Memory Cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 07-07-2011 |
20110189796 | Uniformity in the Performance of MTJ Cells - A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode. | 08-04-2011 |
20110266511 | Phase Change Memory Device with Air Gap - A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided. | 11-03-2011 |
20120091549 | FORMATION OF EMBEDDED MICRO-LENS - Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction. | 04-19-2012 |
20120104339 | PHASE CHANGE MEMORY CELL - On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer. Portions of the electrode layer and the phase change layer are removed by a chemical-mechanical-polishing process to form a phase change region having a remaining portion of the phase change layer and to form an electrode region having a remaining portion of the electrode layer. | 05-03-2012 |
20120211759 | STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER - The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. | 08-23-2012 |
20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
20120261781 | SIDEWALL FOR BACKSIDE ILLUMINATED IMAGE SENSOR METAL GRID AND METHOD OF MANUFACTURING SAME - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 10-18-2012 |
20130026585 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 01-31-2013 |
20130034929 | Method for Forming CMOS Image Sensors - A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed. | 02-07-2013 |
20130043549 | Hole First Hardmask Definition - A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack. | 02-21-2013 |
20130048936 | PHASE CHANGE MEMORY AND METHOD OF FABRICATING SAME - A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer. | 02-28-2013 |
20130234226 | Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. | 09-12-2013 |
20130277778 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING SAME - This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit. | 10-24-2013 |
20140024139 | Hole First Hardmask Definition - A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack. | 01-23-2014 |
20140065756 | Sidewall for Backside Illuminated Image Sensor Metal Grid and Method of Manufacturing Same - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 03-06-2014 |
20140166970 | PHASE CHANGE MEMORY CELL - A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface. | 06-19-2014 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 08-28-2014 |
20140264553 | METHOD OF FABRICATING MONOS SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region. | 09-18-2014 |
20140353794 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF FORMING - A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided. | 12-04-2014 |
20150021725 | MAGNETORESISTIVE RANDOM ACCESS MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion. | 01-22-2015 |
20150031176 | Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 01-29-2015 |
20150048297 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode. | 02-19-2015 |
20150048298 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film. | 02-19-2015 |
20150060750 | Resistance Variable Memory Structure and Method of Forming the Same - A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. | 03-05-2015 |
20150060974 | FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°. | 03-05-2015 |
20150061051 | Magnetic Tunnel Junction Device - A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer. | 03-05-2015 |
20150061052 | Reversed Stack MTJ - An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer. | 03-05-2015 |
20150069619 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. | 03-12-2015 |