Shih-Chang
Shih-Chang Chang, Hsinchu City TW
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20080228510 | METHOD FOR RESERVING EQUIPMENT AND COMPUTER ACCESSIBLE STORAGE MEDIA TO STORE PROGRAM THEREOF - A method for reserving equipment is provided. In the present invention, an arrival time in each site of a special lot is forecasted according to a history record, and the equipment is reserved according to the arrival time and a status of each of the equipments at the site. As a result, suitable equipments in the production line are reserved for the special lot, thus the time of waiting for idle equipment can be eliminated, and the cycle time of processing special lot can be reduced. | 09-18-2008 |
Shih-Chang Chang, Chutung TW
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20100066683 | Method for Transferring Thin Film to Substrate - A method for transferring single layer thin film from a temporary substrate to a target substrate is disclosed. A base layer may be fabricated onto a fabrication sheet. A single layer thin film of conductive material may be patterned onto the base layer. A temporary transfer substrate may be adhered to the single layer thin film. The fabrication sheet may be removed and the base layer-patterned single layer thin film-temporary transfer substrate block transferred to a target substrate, where the base layer may contact the target substrate. Upon completion of the transfer, the temporary transfer substrate may be removed. | 03-18-2010 |
Shih-Chang Chang, Cupetino, CA US
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20140063393 | Displays with Reduced Driver Circuit Ledges - An electronic device display may have a color filter layer, a thin-film-transistor layer, and a layer of liquid crystal material. The display may have a display cover layer such as a layer of glass or plastic. Adhesive may be used to attach the upper polarizer to the display cover layer. The thin-film transistor layer may have a substrate with upper and lower surfaces. Thin-film-transistor circuitry may be formed on the upper surface. A display driver integrated circuit may be mounted to the lower surface or a flexible printed circuit and may be coupled to the thin-film-transistor circuitry using wire bonding wires. Through vias that are formed through the thin-film-transistor layer substrate may be used in coupling the thin-film-transistor circuitry to the display driver integrated circuit. | 03-06-2014 |
Shih-Chang Chang, Jhudong Township TW
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20110070797 | SYSTEM FOR DISPLAYING IMAGES AND METHOD FOR FABRICATING THE SAME - Systems for displaying images and fabrication method thereof are provided. A representative system incorporates an electroluminescent device including light emitting units emitting lights with different luminescent intensities along light emitting paths thereof, formed overlying a substrate. And a compensation layer is disposed along the light emitting paths to adjust the different luminescent intensities for outputting substantially uniform light. | 03-24-2011 |
Shih-Chang Chen, Kinmen County TW
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20130328794 | TOUCH DISPLAY MODULE - A touch display module includes a display device and a first panel. The display device includes a display panel, a frame surrounding the display panel, and at least two first positioning parts disposed on the frame. The first panel is disposed on the display device. The first panel includes a protection plate and at least two second positioning parts disposed on the protection plate. The first positioning parts are combined with the second positioning parts to fix relative locations of the first panel and the display device. | 12-12-2013 |
Shih-Chang Chen, Hokou Township TW
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20110256027 | OZONATED WATER SPRAYING SYSTEM WITH ENERGY RESOURCE CONVERSION, AND OZONATED WATER SPRAYING APPARATUS THEREOF - An ozonated water spraying system with energy resource conversion is disclosed. The system includes an ozonated water spraying apparatus and an energy resource conversion device. The ozonated water spraying apparatus has an ozone generation unit, a mixing and spraying unit, and a water flow detection unit, in which the ozone generation unit is for generating ozone. The mixing and spraying unit couples with the ozone generation unit, for mixing the generated ozone with water and spraying the ozonated water out. Further, the water flow detection unit, coupled to the ozone generation unit and the mixing and spraying unit, is capable of detecting whether water flows through the mixing and spraying unit so as to control the ozone generation unit in response to the detection result. Additionally, the energy resource conversion unit is for converting energy resource into electrical power to provide the requisite power to the ozonated water spraying apparatus. | 10-20-2011 |
Shih-Chang Chen, Hukou Township TW
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20110220229 | WATER SUPPLY APPARATUS OF HYDROTHERAPY SYSTEM - A water supply apparatus of a hydrotherapy device is disclosed. The water supply apparatus includes a motor, a control module, a pressure switch, an ozone module, a first magnetic valve, a second magnetic valve, and a water outlet module. The control module is for driving the motor to retrieve water, and for turning the first magnetic valve and the second magnetic valve on or off and for determining the release of ozone. And by controlling the on/off of the magnetic valves, the operation mode of the water supply apparatus, such as a spa mode and a micro-bubble mode, is changed. Additionally, the control module further includes a leakage detection unit and an overload detection unit, in order to detect a power leakage and a power overload. | 09-15-2011 |
20120080364 | WATER PROVISIONING SYSTEM FOR KITCHEN - The water provisioning system mainly contains a selection switch, a water volume switch, a human-machine interface (HMI), a RO waste water recycling device, an electromagnetic valve, a RO water purification device, an antichlor device, a aeration pipe assembly, a first ozone module, and a second ozone module. The selection switch selects a type of water to use. The RO water purification device filters water from a low-temperature water source, stores purified water in a storage barrel, and provides high-quality drinking water. The 70% water from the RO water purification process that fails the drinking water standard is recycled through the RO waste water recycling device. The low-temperature water source is connected to a antichlor device and the water is therefore dechlorinated. The first and second ozone modules are used to produce ozonated water and to release ozone through the aeration pipe assembly into the kitchen cabinet for deodorization and sterilization. | 04-05-2012 |
Shih-Chang Chen, Miaoli County TW
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20160032233 | AERATION APPARATUS, AERATION METHOD AND CLEANING METHOD - An aeration apparatus, comprising: a gas-liquid mixing-circulating module, a gas supplying module, a controlling module and a cleaning unit, wherein the gas-liquid mixing-circulating module comprises: a first switch valve, connecting to a liquid outlet of a culture tank; a booster pump, connecting to the first switch valve; a micro-bubble producing device, having one end connecting to the booster pump and the other end connecting to a liquid inlet of the culture tank; a first proportional valve; a venturi tube, having a head, a tail and a branch, the other opening of the first proportional valve connecting to the head; and a second proportional valve, having an opening connecting to the tail, and the other opening connecting to the second tube, wherein, a fifth tube transfer gas to the venturi tube through the branch; wherein, the controlling module regulates the gas-liquid mixing-circulating module, the gas supplying module and the cleaning unit. | 02-04-2016 |
Shih-Chang Chen, Hsinchu County TW
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20100132506 | FEED DRIVE MECHANISM AND FLEXIBLE CONNECTION PLATE THEREOF - A flexible connection plate is used in a feed drive mechanism. The flexible connection plate has a first portion, a second portion joined to the first portion, and a plurality of elastic grooves between the first portion and the second portion. The first portion and the second portion are fixed to a nut seat and a lead screw nut of the feed drive mechanism respectively. The elastic grooves are axially penetrating the connection plate. Adjacent elastic grooves have an overlapping section respectively, such that the flexible connection plate has a characteristic of elastic deformation in a radial direction, so as to absorb errors resulted from assembly, and improve non-parallelism resulted from the assembly errors, thereby increasing the feed accuracy of the feed drive mechanism. Furthermore, the rigidity of the flexible connection plate in an axial direction is high enough to drive the feed drive mechanism to be positioned precisely. | 06-03-2010 |
20110036761 | AUTOMATIC OZONE WATER OUTPUT DEVICE - An automatic ozone water output device includes a faucet unit, at least one water inlet pipe, and an ozone generator. The faucet unit will automatically detect the presence of a user to output water. The water inlet pipe having a Venturi section connects the faucet unit and a water source. An ozone generating device having a pressure-sensitive activator is kept in a concealed space or a sheltered location, such as in the area under a basin or a sink. When water flows through the Venturi pipe, a negative pressure is developed and sensed by the pressure-sensitive activator. In response, the pressure-sensitive activator activates the ozone generator, thereby causing the mixing of ozone with the discharged water. | 02-17-2011 |
20110048146 | FEED DRIVE MECHANISM AND CONNECTING ASSEMBLY THEREOF - A feed drive mechanism and a connecting assembly thereof are described. The connecting assembly includes a main body and an outer sleeve. The main body has a connecting plate and an inner sleeve connected to a side surface of the connecting plate. Two opposite side surfaces of the connecting plate are respectively fixed on a screw nut seat and a lead screw nut of the feed drive mechanism, and a channel surrounds an outer side surface of the inner sleeve. The outer sleeve is sleeved on the outer side surface of the inner sleeve, enables the channel to be formed into a sealed space, and has an inlet and an outlet respectively communicating with the channel, thereby injecting a cooling medium into the channel. | 03-03-2011 |
20110114761 | INTEGRATED AERATED BUBBLE GENERATING DEVICE - An aerated bubble generating device, integrated into water-supply means and creating fine bubbles, includes a bubble generation unit, a bubble density-adjustment unit and a water discharge unit. The bubble generation unit has a bubble generation device arranged in the predetermined object and a switch electrically connecting to the bubble generation device and exposed out of the predetermined object. The bubble density-adjustment unit has a bubble density-adjustment device arranged in the predetermined object, for controlling the size of each bubble. The bubble density-adjustment device defines a distal end linking the bubble generation device. The water discharge unit has a water-supply device exposed out of the predetermined object and a communicating pipe linking both of the bubble density-adjustment and the water-supply devices. | 05-19-2011 |
20120266983 | FAUCET DEVICE WITH TOUCH CONTROL AND DISPLAY CAPABILITIES - The present disclosure is related to a faucet device with touch control and display capabilities. The faucet device includes a gas providing unit, a faucet body, and a touch control and display system, wherein the faucet body and the touch control and display system are both coupled to the gas providing unit. The gas providing unit is for providing a predetermined gas to the faucet body, so as to enable the mixing of the predetermined gas with a water flow. The faucet body is equipped with a Venturi tube allowing for the predetermined gas to be transmitted automatically from the gas providing unit to the faucet body when the faucet body is turned on. The predetermined gas may not be transmitted to the faucet body when the water flow does not pass through the Venturi tube. | 10-25-2012 |
20130146516 | AUTOMATIC OZONE WATER OUTPUT DEVICE - An automatic ozone water output device comprises a water supply system, a negative pressure mixing element, and an ozone generating assembly. The water supply system is connected to a water source. The negative pressure mixing element is installed on the water supply system and has at least one flow channel. The ozone generating assembly has a sound sensor and an ozone generator, wherein the sound sensor is in connection with an air source for detecting a sound level of airflow, one end of the ozone generator is in connection with the sound sensor, the other end of the ozone generator is in connection with the negative pressure mixing element. Specially, the negative pressure mixing element is configured in such a way that when water flows through the flow channel, negative pressure is generated to produce an absorbing force to mix ozone into water. | 06-13-2013 |
20140069007 | PLANT GROWTH FACILITATING APPARATUS PLANT GROWTH FACILITATING APPARATUS - A plant growth facilitating apparatus, for receiving and growing a plant, includes an accommodating body and a light emitting unit. The accommodating body defines an accommodating space for receiving the plant. The light emitting unit has a first LED set for emitting a red light in increasing the growth speed of the plant and a second LED set for emitting a blue light in promoting the photosynthesis of the plant. The wavelength range of the red light is 620-760 nanometer, and the wavelength range of the blue light is 360-480 nanometer. The light emitting unit is used for emitting light toward the accommodating space of the accommodating body, and the longest path of the light from the light emitting unit to the accommodating body is smaller than 1 meter. | 03-13-2014 |
20140076724 | CELL MODULE, OZONE GENERATOR THEREOF AND METHODS FOR GENERATING OZONE USING THE SAME - A cell module includes an anode, a cathode and a proton exchange membrane. The anode adheres to one side of the proton exchange membrane while the cathode adheres to the opposite side thereof. The anode comprises a substrate and at least one diamond-like carbon layer covering the substrate. The present disclosure further provides an ozone generator and a method using the same. | 03-20-2014 |
20140251795 | MANUFACTURING METHOD OF CATHODE CATALYST AND OZONE-GENERATING DEVICE - The instant disclosure relates to a manufacturing method of cathode catalyst, comprising the following steps. Initially, mix an organic medium with an iron-based starting material and a nitrogen-based starting material to form a mixture. Followed by adding a carbon material to the mixture and subsequently executing a heating process to form a solid-state precursor. Then mill the solid-state precursor to form a precursory powder. Successively, calcinate the precursory powder in the presence of NH | 09-11-2014 |
20140273197 | VIBRATABLE CULTURE APPARATUS FOR PROVIDING PLANT CELLS WITH GROWTH ENVIRONMENT - A vibratable culture apparatus includes a culture device and a vibrating device having a driving module and a vibrating module. The vibrating module has a working platform connected to the driving module, a plurality of lighting units installed on the working platform, and a plurality of positioning units. The working platform is vibratable in a plane by the driving module. Each lighting unit has a first LED set used and a second LED set. The positioning units are installed on the working platform and respectively arranged adjacent to the lighting units. The culture device is detachably disposed on the working platform and restricted by at least partial the positioning units for maintaining the relative position between the culture device and the working platform. The culture device is arranged above at least partial the lighting units that used for emitting light to penetrate into the culture device. | 09-18-2014 |
20150029333 | NETWORK SURVEILLANCE SYSTEM, WIRELESS NETWORK SURVEILLANCE APPARATUS AND SETTING METHOD THEREOF - A network surveillance system, a wireless network surveillance apparatus, and a setting method of the wireless network surveillance apparatus are provided. The method includes following steps: obtaining at least one connection information for connecting a wireless network surveillance apparatus; connecting the wireless network surveillance apparatus according to the at least one connection information; obtaining an access point (AP) list and displaying the AP list on a user interface unit; after a user selects from the AP list a specific to-be-connected AP through the user interface unit and enters a password corresponding to the specific AP, controlling the wireless network surveillance apparatus to connect the specific AP through a wireless connection according to the password. | 01-29-2015 |
Shih-Chang Chen, Hsinchu County 303 TW
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20120085442 | WATER SUPPLY MODULE FOR HYDROTHERAPY DEVICE - A water supply module for hydrotherapy, which includes a pump, a water inlet, a micro bubble water outlet, a pressurized water outlet, a relief valve, and a mixer. The water inlet is connected to the pump. The micro bubble water outlet and the pressurized water outlet are connected to an outlet of the pump. The relief valve is installed in between the outlet of the pump and the micro bubble water outlet, and the mixer is installed in between the water inlet and the relief valve. A drain valve is further connected off the bottom of the pump to drain out the residual water from the pump and the piping. The integrated water supply module provides space-saving advantage. Furthermore, by draining the residual water, the water supply module also improves SPA hygiene by reducing the risk of skin diseases and infections. | 04-12-2012 |
Shih-Chang Chen, Shinfeng Township TW
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20090150928 | Video apparatus with picture/text messaging function - A video apparatus with a picture/text messaging function includes a multifunctional decoder, a video decoder, an image processor and a display. The multifunctional decoder receives texts, pictures or videos from an external device, and decoding the texts, pictures or videos to output a text signal and an image signal. The video decoder is connected to the multifunctional decoder to receive the image signal and decode the image signal. The image processor is connected to the multifunctional decoder and the video decoder to receive the text signal and the decoded image signal and to output a picture/text messaging signal. The display is connected to the image processor to receive the picture/text messaging signal to display picture and text messages. | 06-11-2009 |
Shih-Chang Chen, Taoyuan TW
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20110318915 | PROCESS TO MAKE HIGH-K TRANSISTOR DIELECTRICS - A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer. | 12-29-2011 |
Shih-Chang Chen, Hsinchu TW
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20080230814 | Methods for fabricating a semiconductor device - A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH | 09-25-2008 |
20120085949 | FLUID TRANSPORTATION DEVICE - A fluid transportation device includes a valve seat, a valve cap, a valve membrane, and an actuating module. The valve seat has an outlet channel and an inlet channel. The valve cap has a tilt structure. The valve membrane has an inlet valve structure and an outlet valve structure. The actuating module has a vibration film and an actuator. When the fluid transportation device is in a non-actuation status, a pressure cavity with a gradually-increasing depth is defined. When a voltage is applied on the actuator to result in deformation of the actuator, the vibration film generates a pressure difference to push the fluid. The fluid is introduced into the inlet valve structure through the inlet channel, guided by the tilt structure of the valve cap to be flowed from the pressure cavity to the outlet valve structure, and then flowed out of the outlet channel. | 04-12-2012 |
20120090710 | CLOSED NEBULIZING SYSTEM FOR REMOVING BUBBLES - A closed nebulizing system for removing bubbles includes a first pump, a nebulizing module and a second pump. The first pump is for providing a fluid. The nebulizing module includes an outlet channel, an inlet channel connected with the first pump, and a plurality of nozzles for nebulizing and ejecting part of the fluid. The second pump is connected with the outlet channel for outputting non-nebulized fluid. The first pump, the nebulizing module and the second pump form a closed fluid loop, so that the fluid continuously contacts with the plurality of nozzles and bubbles generated during nebulization process are evacuated from the nebulizing module. | 04-19-2012 |
20120092399 | POWER SUPPLY INTEGRATED CIRCUIT FOR PIEZOELECTRIC INKJET HEAD - A power supply integrated circuit includes a DC-DC boost regulating unit and a DC-AC output controlling unit. The DC-DC boost regulating unit is used for increasing a low DC voltage into a high DC voltage. The DC-AC output controlling unit is connected with the DC-DC boost regulating unit for converting the high DC voltage into a high AC voltage. A first portion of an integrated circuit chip and a plurality of passive components are collaboratively defined as the DC-DC boost regulating unit. A second portion of the integrated circuit chip is defined as the DC-AC output controlling unit. | 04-19-2012 |
20120092418 | SINGLE-NOZZLE INKJET HEAD - A single-nozzle inkjet head includes a first chamber member and a second chamber member. The first chamber member has a first flow channel. The second chamber member is detachably connected with the first chamber member. The second chamber member includes a main body, a nozzle plate and an actuator. The main body has a second flow channel, wherein the second flow channel is in communication with the first flow channel for transporting a fluid. The nozzle plate is disposed on the main body, and has a nozzle. The actuator is disposed on the nozzle plate, and located around the nozzle. | 04-19-2012 |
20120094485 | METHOD OF FORMING CONTACTS FOR A SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other. | 04-19-2012 |
20130043765 | POLARITY SWITCHING CIRCUIT - A polarity switching circuit includes: a first current-limiting resistor and a second current-limiting resistor connected to a DC high voltage; a first transistor switch, a second transistor switch, a fourth transistor switch, and a fifth transistor switch respectively controlled by a first PWM signal and a second PWM signal; a third transistor and a sixth transistor switch whose control terminals are respectively connected to the first transistor switch and the fourth transistor switch; a first filter connected to the second transistor switch and the third transistor switch and a contact of a piezoelectric actuator; and a second filter connected to the fifth transistor switch and the sixth transistor switch and another contact of the piezoelectric actuator. When the first and the second PWM signal are switching between a high level and a low level, output AC voltages with smoothed AC waveforms are supplied to the contacts of the piezoelectric actuator. | 02-21-2013 |
20140042872 | POLARITY SWITCHING CIRCUIT - A polar switch circuit is disclosed. The polar switch circuit comprises the first to the forth transistor switches and the first to the second filter circuits. The first and forth transistor switches are controlled by a first pulse-width modulating signal. The second and third transistor switches are controlled by a second pulse-width modulating signal. The second and the fourth transistor switches are connected with a DC high voltage, and connected with the first and third transistor switches, respectively. The first filter circuit is connected with the first transistor switch, the second transistor switch and a contact of a piezoelectric actuator. The second filter circuit is connected with the third transistor switch, the forth transistor switch and another contact of the piezoelectric actuator. When the first and second pulse-width modulating signals switch high/low level in interlaced, an output AC voltage can be smooth and deliver to the contacts of the piezoelectric actuator. | 02-13-2014 |
20140377099 | MICRO-GAS PRESSURE DRIVING APPARATUS - A micro-gas pressure driving apparatus includes a miniature gas transportation module and a miniature valve module. The miniature gas transportation module includes a gas inlet plate, a fluid channel plate, a resonance membrane and a piezoelectric actuator. A first chamber is defined between the resonance membrane and the piezoelectric actuator. After the piezoelectric actuator is activated to feed a gas through the gas inlet plate, the gas is transferred to the first chamber through the fluid channel plate and the resonance membrane and then transferred downwardly. Consequently, a pressure gradient is generated to continuously push the gas. The miniature valve module includes a gas collecting plate, a valve membrane and a gas outlet plate. After the gas is transferred from the miniature gas transportation module to the gas-collecting chamber, the gas is transferred in one direction, so that a pressure-collecting operation or a pressure-releasing operation is selectively performed. | 12-25-2014 |
20160076530 | MICRO-GAS PRESSURE DRIVING DEVICE - A micro-gas pressure driving device includes a miniature gas transportation module, a covering plate and a tube plate. The miniature gas transportation module includes a convergence plate, a resonance membrane and a piezoelectric actuator. When the piezoelectric actuator is activated to feed a gas into an input tube of the tube plate, the gas is sequentially transferred through a first input chamber, a second input chamber, an inlet, a convergence channel and a central opening of the convergence plate, a central aperture of the resonance membrane, and transferred downwardly through the piezoelectric actuator and an output chamber, and outputted from an output tube of the tube plate. The first input chamber is arranged between the covering plate and the input tube. The second input chamber is defined between the covering plate and the convergence plate. The output chamber is defined between the tube plate and the piezoelectric actuator. | 03-17-2016 |
Shih-Chang Chen, Changhua County TW
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20120173132 | VEHICLE EMISSION MONITORING DEVICE AND METHOD THEREOF - The present invention discloses a vehicle emission monitoring device and a method thereof. The method of the present invention comprises steps: obtaining an OBS instantaneous fuel consumption and a carbon dioxide emission from an on-board emission measurement system (OBS); working out an OBS fuel consumption-carbon dioxide emission relationship with a statistical method or a regression method; obtaining an OBD instantaneous fuel consumption from an on-board diagnostic (OBD) system; establishing an OBS-OBD fuel consumption relationship; and converting the OBD instantaneous fuel consumption into an carbon dioxide emission according to the OBS-OBD fuel consumption relationship and the OBS fuel consumption-carbon dioxide emission relationship. | 07-05-2012 |
Shih-Chang Chen, Sinfong Township TW
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20090150952 | Video apparatus with web processing function and method for web display - A video apparatus with webpage processing function is provided. The present invention comprises a TV signal receiver module, a network connection module, an video processing module, and a display module. The network connection module is used for connecting to the Internet via a network point to capture a web frame. The video processing module is used for receiving a web frame through the network connection module and for receiving a TV frame through the TV signal receiver module, and then outputs the web frame or TV frame to a display module when the network connection module connects to the Internet. | 06-11-2009 |
20100107195 | Program preference setting method and system for a broadcasting video program - A program preference setting method and system for broadcasting video program are disclosed. The preference setting method and system are generally applied to an Electronic Program Guide (EPG) for the digital television program. More particularly, a program preference setting system is provided to be embedded in the digital broadcast program receiving and playing device. One or more keywords may be set to the electronic program guide. Through comparison between the keyword(s) and the content of EPG, the positive comparison result is found for scheduling a program sequence. Further, a reminder corresponding to the program sequence may be set in a certain period through the system, and shown on the screen for user's convenience. | 04-29-2010 |
Shih-Chang Chiu, Nantou County TW
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20100225530 | METHOD OF HANDLING RADAR SIGNALS FOR A WIRELESS COMMUNICATION DEVICE - A method of handling radar signals for a wireless communication device includes operating the wireless communication device in a listening mode to detect the radar signals on a first channel for a listening time period, operating the wireless communication device in an idle mode when the radar signal is not detected on the first channel during the listening time period, starting an idle timer when the wireless communication device is operated in the idle mode, sending at least one clear-to-send frame when the idle timer expires, and operating the wireless communication device in a waiting mode to make sure the at least one clear-to-send frame is completely sent within a waiting time period. | 09-09-2010 |
Shih-Chang Chu, Taoyuan TW
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20100283057 | PIXEL STRUCTURE - A pixel structure is provided. A data line and a scan line are disposed over a substrate. A first, a second, and a third thin film transistors (TFT) are electrically connected with the data line and the scan line respectively. A first width-to-length ratio, a second width-to-length ratio and a third width-to-length ratio of the first, second and third TFTs are the same. An impedance layer and the first TFT are connected in series. A first, a second, and a third pixel electrodes are electrically connected with the first, the second and the third TFTs respectively. A first, a second, and a third common line are disposed below the first, second and third pixel electrodes respectively. The first and second common lines are electrically connected to a first voltage and the third common line is electrically connected to a second voltage. | 11-11-2010 |
Shih-Chang Chuang, Taoyuan Hsien TW
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20130314865 | POWER SUPPLY APPARATUS AND MODULAR POWER CONNECTING METHOD THEREOF - A power supply apparatus includes a first electronic device, a second electronic device, and plural power modules. The first electronic device includes a first compartment. The first compartment has a first width. The second electronic device includes a second compartment. The second compartment has a second width. Each of the power modules has a third width. The third width is determined according to the first width and the second width, so that a specified number of power modules are selectively accommodated within the first compartment or the second compartment. | 11-28-2013 |
Shih-Chang Hsieh, Tainan City TW
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20120245713 | PLATFORM AND METHOD FOR BCI CONTROL - A method for BCI control is utilized to control a plurality of brain control devices. The brain control devices are capable of executing an operation themselves. A brain-wave control platform is provided for supplying a first signal and a second signal, wherein the first and second signals are utilized to visually evoke a user's first and second brain waves, respectively. The brain-wave control platform selects one of the brain control devices as a to-be-controlled device by the first brain wave, and the to-be-controlled device is controlled to finish an operation by the second brain wave. | 09-27-2012 |
Shih-Chang Hsu, Taipei City TW
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20100131327 | COLLABORATIVE METHOD AND ITS IMPLEMENTATION SYSTEM FOR A TRUST-BASED BUSINESS COMMUNITY - A collaborative method and its implementation system for a trust-based business community, enables a business person, who behaves as a function of a corporation, to invite his/her business partners to form a trust-based business community. Through this method and system, the business person can create, conduct and commit/abort a collaborative activity with their business partners to achieve a business objective. This method and system are also defined as a participation mechanism, which effectively addresses the mixed situations of competition and collaboration. Based on legal-binding invitation and principle of good faith, the system can support the establishment of such a TBC, thus providing a good collaboration platform for the companies to do business effectively and efficiently in today's business world. The key application of this method and system is for Collaborative Sourcing and Product Development, which helps a buyer to source and develop products with multiple suppliers in a single process, wherein some suppliers may be competitive to each others and some are collaborative to each others. | 05-27-2010 |
Shih-Chang Hsu, Tu-Cheng TW
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20100232791 | COMMUNICATION DEVICE AND LIGHT GUIDING MEMBERS USED THEREIN - A communication device includes an enclosure including a recess member including a bottom wall and an accommodating portion, a circuit board mounted on the bottom wall, and a light guiding member received in the accommodating portion. The circuit board includes a plurality of light sources arranged in a circular array. The light guiding member includes a light guiding portion to transmit light from the light sources to an outer surface of the communication device and a light shielding portion to shield the light to the outer surface and fix the light guiding portion in the accommodating portion. The light guiding portion includes a light guiding bottom wall surrounding the light sources and a light guiding sidewall. The light guiding sidewall includes an annular end surface to indicate signal strength and a strong signal orientation received by an antenna of the communication device. | 09-16-2010 |
20110259890 | ENCLOSURE OF OUTDOOR APPARATUS - An enclosure of an outdoor apparatus includes a first case, a second case and a gasket ring sealed between the first case and the second case. The first case includes a first cover and a flange portion extending from the first cover outwardly. The first case defines a first open surrounded by the flange portion. The flange portion defines a latching groove towards the first open. The second case includes a second cover and a stopper portion extending from the second cover outwardly. The stopper portion is received in the first open and matches with the flange portion. The cover defines a second open surrounded by the stopper portion and opposite to the first open. The stopper portion includes a latch portion protruded outwardly from the stopper portion to engage with the latching groove. | 10-27-2011 |
20130025932 | WATERPROOF ASSEMBLY AND DEVICE EMPLOYING THE SAME - A device includes a cover defining a sleeve allowing a transmission cable pass through to communicate inner with outer of the device. An elastomer is filled in the sleeve and embedded with the transmission cable. A fastening member is employed to engaged with the sleeve to tightly press the elastomer embedded with the transmission cable to prevent water from entering into the device along the transmission cable and the sleeve. | 01-31-2013 |
Shih-Chang Hsu, Taipei TW
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20120224360 | ILLUMINATION LAMP - An illumination lamp comprises a lamp body, a light-emitting module, a power supply module, and a circuit module. The lamp body defines an inner space. The partitioning unit is disposed in the lamp body for dividing the inner space into a first space for receiving the power supply module, and a second space for receiving the circuit module. Due to the presence of the partitioning unit, thermal convection between the first and second spaces is prevented to reduce adverse influence of a high temperature of the circuit module on the power supply module. | 09-06-2012 |
20120230026 | LUMINAIRE HAVING INNER FLOW PATH - A luminaire includes a base, a light-emitting unit, and a lamp cover. The base includes a first tube part, a second tube part having an inner diameter smaller than that of the first tube part, and a joint part connected between the first and second tube parts. An inner flow path is defined by at least the first tube part, the joint part, and the second tube part in a coaxial manner. The lamp cover is fixed on the base for covering the light-emitting unit. As such, air heated by the light-emitting unit flows out of the inner flow path to thereby allow cold air to be sucked into the inner flow path. | 09-13-2012 |
20130238664 | LARGE-SCALE DATA PROCESSING SYSTEM, METHOD, AND NON-TRANSITORY TANGIBLE MACHINE-READABLE MEDIUM THEREOF - A large-scale data processing system, a large-scale data processing method, and a non-transitory tangible machine-readable medium are provided. The large-scale data processing system comprises an interface and a processor. The interface accesses a multi-dimensional data model, wherein the multi-dimensional data model comprises a plurality of dimensions, the dimensions form a multi-dimensional space of measures, each dimension is a single space comprising a plurality of members with a common set of attributes, and each measure is a data element organized and accessible through the multi-dimensional space of the cross-product of all dimensions. The processor builds at least one Tree Object (TO), wherein the TO is derived by converting the multi-dimensional data model into an N-level tree data structure according to a level order of N attributes, each tree node in the TO meets all conditions of attributes for all ancestor nodes, and N is a positive integer. | 09-12-2013 |
20130270588 | LEAD FRAME ASSEMBLY, LED PACKAGE AND LED LIGHT BAR - A lead frame assembly includes a surrounding frame and a plurality of lead frame sets arranged in a matrix. Each lead frame set includes spaced-apart first and second lead frames and a connecting structure interconnecting one of the lead frame sets to an adjacent lead frame set. Each lead frame set is further connected to the surrounding frame through the connecting structure thereof. A plurality of insulated bars are spacedly formed on a lead frame panel. Each insulated bar covers a corresponding row of the lead frame sets and exposes bottom surfaces of the first and second lead frames. Each insulated bar further covers portions of the surrounding frame that are adjacent to two opposite outermost ones of the lead frame sets. | 10-17-2013 |
20150034986 | LED PACKAGE - An LED package includes a chip carrier, an adhesive layer, one high-voltage LED die, and an encapsulating member. The chip carrier defines a receiving space. The adhesive layer is disposed in the receiving space and has a thermal conductivity of larger than or equal to 1 W/mK. The high-voltage LED die is attached to the adhesive layer to be received in the reflective space and has a top surface formed with a trench. The trench of the high-voltage LED die is disposed at an optical center of the receiving space. The encapsulating member encapsulates the high-voltage LED die and includes a plurality of diffusers. The trench is embedded with the encapsulating member and has a width ranging from 1 μm to 10 μm and a depth of less than or equal to 50 μm. | 02-05-2015 |
Shih-Chang Hu, Hsin-Chu City TW
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20090204735 | SYSTEMS AND METHODS FOR SELECTIVELY ACTIVATING FUNCTIONS PROVIDED BY A MOBILE PHONE - Methods for selectively activating one of multiple functions provided by a mobile phone are provided. An embodiment of a method for selectively activating one of multiple functions comprises the following steps. That the mobile phone has been coupled to a computer system is detected. A first interface is displayed to facilitate selection of a first function from the functions. That the first function is selected is detected by the first interface. At least one software module is configured to activate the first function, thereby the computer system is directed to employ the mobile phone as a first external electronic device corresponding to the first function. | 08-13-2009 |
20090290636 | VIDEO ENCODING APPARATUSES AND METHODS WITH DECOUPLED DATA DEPENDENCY - Video encoding apparatuses and methods with decoupled data dependency are provided. An embodiment of a method for video encoding with decoupled data dependency contains at least steps as follows. Data generated from a macroblock of a previous frame is acquired. At least one reference parameter for a macroblock of a current frame is determined according to the acquired data. The macroblock of the current frame is encoded according to the determined reference parameter to generate an output bitstream. | 11-26-2009 |
20090323810 | VIDEO ENCODING APPARATUSES AND METHODS WITH DECOUPLED DATA DEPENDENCY - The invention provides an apparatus for video encoding with decoupled data dependency. In one embodiment, the apparatus comprises a buffer, a hardware circuit, and a parameter determination module. The hardware circuit, coupled to the buffer, generates and stores data during performing motion estimation on a current frame and encoding a plurality of macroblocks of the current frame in the buffer. The parameter determination module, coupled to the hardware circuit and the buffer, retrieves the stored data from the buffer, generates at least one reference parameter for a plurality of macroblocks of a future frame according to the retrieved data, and updates data of the buffer with the generated reference parameters after receiving a triggering signal indicating start of data preparation for the future frame from the hardware circuit. | 12-31-2009 |
20100159989 | CELLULAR PHONE AND PORTABLE STORAGE DEVICE USING THE SAME - A cellular phone. The cellular phone comprises a connector, a first memory module, a second memory module, and a controller. The connector is used for physically connecting the cellular phone to an external device. The first memory module stores phone data. The second memory module stores application data received from the external device. The controller determines whether the connector is connected to the external device. If the connector is not connected to the external device, access right of both the first and second memory modules is granted exclusively to the cellular phone. If the connector is connected to the external device, access right of the first memory is granted exclusively to the cellular phone, and access right of the second memory module is granted exclusively to the external device. | 06-24-2010 |
Shih-Chang Kuo, Taipei City TW
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20100117956 | DISPLAY SYSTEM AND METHOD FOR CONTROLLING AN ON-SCREEN DISPLAY WITHIN A DISPLAY SCREEN - A display system is used for controlling an on-screen display within a display device. The on-screen display is a text information including a literal string formed by combining several numbers of letters. The display system includes a memory device for storing pieces of letter information, a controller to download a coding chart upon initialization of the display device. The coding chart includes string-forming codes and letter-forming codes. The coding chart further includes groups of string-forming codes for encoding different literal strings. The string-forming codes and the letter-forming codes correspond to the letter information in the memory. Upon receipt of an external command corresponding to a specific string-forming code, the controller fetches a letter-forming code from the coding chart based on the specific string-forming code and letter information from the memory device based on the respective letter-forming code, thereby encoding and displaying the literal string over the display screen. | 05-13-2010 |
Shih-Chang Liang, Taoyuan City TW
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20160047033 | LINEAR EVAPORATION APPARATUS FOR IMPROVING UNIFORMITY OF THIN FILMS AND UTILIZATION OF EVAPORATION MATERIALS - A linear evaporation apparatus includes a thermal insulation chamber, and crucibles, evaporation material heaters and a mixing chamber installed in the thermal insulation chamber. The mixing chamber includes a flow limiting and adjusting layer, a flow channel adjusting member, a mixed layer and a linear evaporation layer. The flow limiting and adjusting layer is a rectangular sheet with flow limit holes corresponsive to the crucibles respectively; the flow channel adjusting member is an interconnected structure having at least one flow inlet corresponsive to some of the flow limit holes and at least one flow outlet, and the mixed layer is a substantially I-shaped sheet structure, and the linear evaporation layer is a rectangular sheet having a linear source evaporation opening tapered from both ends to the middle, so as to improve the uniformity of the thin film and the utilization of the evaporation materials. | 02-18-2016 |
20160097117 | METHOD AND APPARATUS FOR STABLY EVAPORATION DEPOSITING UNIFORM THIN FILMS - In a method and apparatus for evaporation depositing uniform thin films, a film is deposited on a substrate of a vacuum environment while maintaining a constant deposition rate. A cover is installed on a wall of the evaporation vessel. When the evaporation material is heated to an evaporation state and the interior of the evaporation vessel reaches a first vapor saturation pressure, the vapor of the evaporation material flows towards a pressure stabilizing chamber. When the pressure stabilizing chamber reaches a second vapor saturation pressure which is smaller than the first vapor saturation pressure, the vacuum environment has a vacuum background pressure which is smaller than the second vapor saturation pressure, so that the evaporation material vapor flows from the pressure stabilizing chamber towards the vacuum environment at constant rate due to the pressure difference, so as to evaporate the substrate. | 04-07-2016 |
Shih-Chang Liang, Chutung TW
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20080224545 | PULSE GENERATING DEVICE AND METHOD - A pulse generating device and method are provided. The pulse generating device includes a control device, a first knob, and a second knob. The control device is configured to receive a pulse signal and generate a pulse command. After being actuated, the first knob provides a single pulse of the pulse signal to the control device for triggering the control device to generate a single pulse command. The second knob provides the pulse signal to the control device in a frequency corresponding to a twisted angle of the second knob so as to trigger the control device to repeatedly generate the pulse command. | 09-18-2008 |
Shih-Chang Liang, Changhua County TW
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20090140683 | REHABILITATION ROBOT AND TUTORIAL LEARNING METHOD THEREFOR - The present invention relates to a rehabilitation robot and a tutorial learning method for the rehabilitation robot. The rehabilitation robot comprises a robotic device, a rehabilitation mode control unit, and a driving unit. The robotic device comprises at least a motor capable of controlling the joints of the robotic device. The rehabilitation mode control unit further comprises a tutorial learning module capable of enabling the rehabilitation robot to learn a rehabilitation operation of a physiotherapist in a tutorial manner as he/she is operating the rehabilitation robot while registering the rehabilitation operation as an operation mode of the same. When the rehabilitation robot is used for performing a therapeutic session on a patient and a tutorial learning mode is selected for the rehabilitation robot, it is required to have a physiotherapist operate the rehabilitation robot and the same time that the rehabilitation robot will register motor actuation parameters corresponding to the therapeutic session into the tutorial learning module. On the other hand, when an automatic rehabilitation mode is selected, the rehabilitation robot will access the motor actuation parameters registered in the tutorial learning module so as to reproduce the therapeutic session simulating the physiotherapist. | 06-04-2009 |
Shih-Chang Lin, Taipei TW
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20110184741 | DEVICE, METHOD AND SYSTEM FOR VIRTUAL BUSINESS OPERATION BASED ON POSITIONING TECHNOLOGY - A positioning-based virtual business operation system includes a seller equipment having a positioning device for acquiring positioning information of the seller equipment and a data transmitting/receiving device for transmitting the positioning information; an operation platform having a business information interface for receiving the positioning information of the seller equipment and updating location information of the seller equipment in the business information interface; and an operator equipment for transmitting operation service information to the operation platform via a network and adjusting service information of the seller equipment or operator information in the business information interface, thereby allowing consumers, mobile sellers, operators of virtual business, and operators of portal sites to benefit from the system and thus creating an all-beneficial business running pattern. | 07-28-2011 |
Shih-Chang Lin, Hsinchu TW
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20130280296 | DNA VACCINE AGAINST MULTITYPES OF AVIAN INFLUENZA VIRUSES AND INFLUENZA VIRUS-LIKE PARTICLES COMPRISING ADJUVANT-FUSED M2 PROTEIN - A DNA vaccine comprising hyperglycosylated mutant HA gene, which is derived from avian influenza virus, is provided. A DNA vaccine composition comprising: (a) the DNA vaccine; and (b) a booster is also provided. An influenza virus-like particle comprising adjuvant-fused M2 protein is further provided. A method for eliciting an immune response against a plurality of avian influenza virus subtypes in a subject, comprising delivering the DNA vaccine or the DNA vaccine composition to tissue of the subject is also provided | 10-24-2013 |
20140193448 | VACCINE AGAINST MULTITYPES OF AVIAN INFLUENZA VIRUSES AND USES THEREOF - The present invention relates to a recombinant DNA molecule encoding a mutated hemagglutinin protein, wherein the mutated hemagglutinin protein consists of the amino acid sequence of SEQ ID NO: 2 with one or more mutations at amino acid residue selecting from the group consisting of residue 83, 127, 138 and the combination thereof. The present invention also relates to a composition comprising the recombinant DNA molecule as described above and a pharmaceutically or veterinarily acceptable carrier, excipient, adjuvant, or vehicle. The present invention further relates to a kit for prime-boost vaccination, comprising at least a composition comprising a recombinant DNA molecule as described above and at least a composition for the boost-vaccination comprising a recombinant hemagglutiinin protein or a virus-like particle, wherein the recombinant hemagglutiinin protein is the corresponding hemagglutiinin protein encoded by the recombinant DNA molecule. The present invention still further relates to a method of vaccinating a subject susceptible to avian influenza comprising administrating to the subject an effective amount of the composition as described above. The present invention still further relates to a recombinant hemagglutinin protein consisting of the amino acid sequence of SEQ ID NO: 2 with one or more mutations at amino acid residue selecting from the group consisting of residue 83, 127, 138, and the combination thereof. | 07-10-2014 |
Shih-Chang Lin, Taichung TW
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20150040407 | CUTTING TOOL - A cutting tool is revealed. The cutting tool includes an upper handle, a lower handle, a blade, at least one quick release device and a connection part. The cutting tool features on that both the blade and the connection part are pivoted quickly by the quick release device without any special tools. When the cutting tool is in an open state or a closed state, the quick release device disposed on the connection part is switched and moved in a circular part on one end of the blade so as to cut. | 02-12-2015 |
Shih-Chang Lin, Kaohsiung TW
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20150322274 | THERMALLY CURABLE SOLDER-RESISTANT INK AND METHOD OF MAKING THE SAME - A method of making a thermally curable solder-resistant ink, which comprises the following steps: polymerizing an aliphatic diamine monomer having a long carbon chain, an aromatic dianhydride monomer, an aromatic diamine monomer having a carboxylic group, and an anhydride monomer having a carboxylic group in an aprotic solvent to obtain a polyamine acid; cyclizing the polyamine acid to obtain a modified polyimide; and mixing the modified polyimide and a curing agent to obtain the thermally curable solder-resistant ink. By the steps mentioned above, the thermally curable solder-resistant ink made from the method has a dielectric constant less than 3.00 and a dielectric loss less than 0.01 and thereby is applicable to high frequency electronic equipments. Also, the thermally curable solder-resistant ink has good electrical properties, folding endurance, solder resistance, warpage resistance, flame resistance, acid endurance, alkali endurance, good solvent resistance and low water absorption. | 11-12-2015 |
Shih-Chang Lin, Tainan City TW
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20160005860 | INTEGRATED FABRICATION OF SEMICONDUCTOR DEVICES - In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region. | 01-07-2016 |
Shih-Chang Lin, Hsinchu City TW
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20110182312 | LASER DIODE USING ASYMMETRIC QUANTUM WELLS - A laser diode using asymmetric quantum wells includes a N-type semiconductor, a P-type semiconductor, a first quantum well structure, and a second quantum well structure. The first quantum well structure is between the N-type semiconductor and the P-type semiconductor, and includes at least one first quantum well having a first thickness. The second quantum well structure is between the N-type semiconductor and the P-type semiconductor, and includes at least one second quantum well having a second thickness greater than the first thickness of the first quantum well and a lasing wavelength greater than that of the first quantum well. The second quantum well is formed with a spike therein. | 07-28-2011 |
Shih-Chang Liu, Yuku Village TW
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20140110823 | CONTACT STRUCTURE - One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example. | 04-24-2014 |
Shih-Chang Liu, Kaohsiung City TW
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20150145022 | CMP FABRICATION SOLUTION FOR SPLIT GATE MEMORY EMBEDDED IN HK-MG PROCESS - A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate. | 05-28-2015 |
20150263015 | FLASH MEMORY STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer. | 09-17-2015 |
20150280004 | EMBEDDED NONVOLATILE MEMORY - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 10-01-2015 |
20150364482 | EMBEDDED NONVOLATILE MEMORY AND FORMING METHOD THEREOF - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 12-17-2015 |
Shih-Chang Liu, Alian Township TW
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20080217675 | Novel profile of flash memory cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 09-11-2008 |
20080248620 | Gated semiconductor device and method of fabricating same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 10-09-2008 |
20090026432 | METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE - A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process. | 01-29-2009 |
20090029547 | NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION - A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps. | 01-29-2009 |
20110006355 | Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. | 01-13-2011 |
20110165746 | Novel Profile of Flash Memory Cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 07-07-2011 |
20110189796 | Uniformity in the Performance of MTJ Cells - A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode. | 08-04-2011 |
20110266511 | Phase Change Memory Device with Air Gap - A semiconductor device is provided which includes a bottom electrode contact formed on a substrate, and a dielectric layer formed on the bottom electrode contact. The device further includes a heating element formed in the dielectric layer, wherein the heating element is disposed between two air gaps separating the heating element from the dielectric layer, and a phase change element formed on the heating element, wherein the phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. A method of forming such a device is also provided. | 11-03-2011 |
20120091549 | FORMATION OF EMBEDDED MICRO-LENS - Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction. | 04-19-2012 |
20120104339 | PHASE CHANGE MEMORY CELL - On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer. Portions of the electrode layer and the phase change layer are removed by a chemical-mechanical-polishing process to form a phase change region having a remaining portion of the phase change layer and to form an electrode region having a remaining portion of the electrode layer. | 05-03-2012 |
20120211759 | STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER - The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. | 08-23-2012 |
20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
20120261781 | SIDEWALL FOR BACKSIDE ILLUMINATED IMAGE SENSOR METAL GRID AND METHOD OF MANUFACTURING SAME - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 10-18-2012 |
20130026585 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 01-31-2013 |
20130034929 | Method for Forming CMOS Image Sensors - A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed. | 02-07-2013 |
20130043549 | Hole First Hardmask Definition - A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack. | 02-21-2013 |
20130048936 | PHASE CHANGE MEMORY AND METHOD OF FABRICATING SAME - A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer. | 02-28-2013 |
20130234226 | Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. | 09-12-2013 |
20130277778 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING SAME - This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit. | 10-24-2013 |
20140024139 | Hole First Hardmask Definition - A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack. | 01-23-2014 |
20140065756 | Sidewall for Backside Illuminated Image Sensor Metal Grid and Method of Manufacturing Same - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 03-06-2014 |
20140166970 | PHASE CHANGE MEMORY CELL - A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface. | 06-19-2014 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 08-28-2014 |
20140264553 | METHOD OF FABRICATING MONOS SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate structures having asymmetric sidewalls including a tall side and a short side. Adjacent ones of the plurality of gate structures are separated by a tall side-tall side region and a short side-short side region. The method further comprises forming a spacer layer over the plurality of gate structures and a bottom surface of the tall side-tall side region and the short side-short side region, depositing an oxide layer over the spacer layer, etching the bottom surface portions of the oxide layer, and selectively etching the sidewall portions of the oxide layer in the tall side-tall side region. | 09-18-2014 |
20140353794 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF FORMING - A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided. | 12-04-2014 |
20150021725 | MAGNETORESISTIVE RANDOM ACCESS MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion. | 01-22-2015 |
20150031176 | Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 01-29-2015 |
20150048297 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface, a second electrode having a lower surface directly over the upper surface of the first electrode, a resistance variable film between the first electrode and the second electrode, and a first conductive member on and surrounding an upper portion of the second electrode. | 02-19-2015 |
20150048298 | MEMORY CELL HAVING RESISTANCE VARIABLE FILM AND METHOD OF MAKING THE SAME - A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film. | 02-19-2015 |
20150060750 | Resistance Variable Memory Structure and Method of Forming the Same - A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. | 03-05-2015 |
20150060974 | FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°. | 03-05-2015 |
20150061051 | Magnetic Tunnel Junction Device - A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer. | 03-05-2015 |
20150061052 | Reversed Stack MTJ - An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer. | 03-05-2015 |
20150069619 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. | 03-12-2015 |
20150091071 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 04-02-2015 |
20150091072 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 04-02-2015 |
20150097216 | SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE - A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region. | 04-09-2015 |
20150097218 | SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE - A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region. | 04-09-2015 |
20150097223 | METHOD AND APPARATUS FOR CONTROLLING GATE DIMENSIONS OF MEMORY DEVICES - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 04-09-2015 |
20150137206 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 05-21-2015 |
20150145100 | SEMICONDUCTOR ARRANGMENT WITH CAPACITOR - A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor. | 05-28-2015 |
20150145101 | SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR - A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion. | 05-28-2015 |
20150147825 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 05-28-2015 |
20150155293 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 06-04-2015 |
20150162329 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density. | 06-11-2015 |
20150187777 | SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall. | 07-02-2015 |
20150236030 | Split Gate Memory Device and Method of Fabricating the Same - The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them. | 08-20-2015 |
20150236110 | SPLIT GATE CELLS FOR EMBEDDED FLASH MEMORY - In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer. | 08-20-2015 |
20150255713 | Resistance Variable Memory Structure and Method of Forming the Same - A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. | 09-10-2015 |
20150255718 | RRAM CELL STRUCTURE WITH CONDUCTIVE ETCH-STOP LAYER - The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode. | 09-10-2015 |
20150263010 | Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary. | 09-17-2015 |
20150270363 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 09-24-2015 |
20150279849 | SILICON NITRIDE (SiN) ENCAPSULATING LAYER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation. | 10-01-2015 |
20150295005 | DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSORS - Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench. | 10-15-2015 |
20150295172 | RRAM Cell with Bottom Electrode - The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for low leakage currents within the RRAM cell without using insulating sidewall spacers, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A bottom dielectric layer is disposed over the lower metal interconnect layer and/or the lower ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the dielectric data storage layer onto the bottom dielectric layer increases a leakage path distance between the bottom and top electrodes, and thereby provides for low leakage current for the RRAM cell. | 10-15-2015 |
20150311296 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 10-29-2015 |
20150311435 | Leakage Resistant RRAM/MIM Structure - An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents. | 10-29-2015 |
20150333173 | SPLIT GATE MEMORY DEVICES AND METHODS OF MANUFACTURING - Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device. | 11-19-2015 |
20150340493 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 11-26-2015 |
20150340596 | Magnetic Tunnel Junction Device - A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer. | 11-26-2015 |
20150364558 | SPLIT GATE FLASH MEMORY STRUCTURE AND METHOD OF MAKING THE SPLIT GATE FLASH MEMORY STRUCTURE - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided. | 12-17-2015 |
20150372121 | ASYMMETRIC FORMATION APPROACH FOR A FLOATING GATE OF A SPLIT GATE FLASH MEMORY STRUCTURE - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided. | 12-24-2015 |
20150372136 | Pattern Layout to Prevent Split Gate Flash Memory Cell Failure - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided. | 12-24-2015 |
20150380568 | Split Gate Flash Memory Structure with a Damage Free Select Gate and a Method of Making the Split Gate Flash Memory Structure - A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided. | 12-31-2015 |
20160028000 | MRAM Device and Fabrication Method Thereof - A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction. | 01-28-2016 |
20160035817 | Process to Improve Performance for Metal-Insulator-Metal (MIM) Capacitors - Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions. | 02-04-2016 |
20160043097 | SELF-ALIGNED SPLIT GATE FLASH MEMORY - The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have flat upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced. | 02-11-2016 |
20160043306 | REVERSED STACK MTJ - An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer. | 02-11-2016 |
20160049420 | COMPOSITE SPACER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact. | 02-18-2016 |
20160056250 | Recessed Salicide Structure to Integrate a Flash Memory Device with a High K, Metal Gate Logic Device - Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad. | 02-25-2016 |
20160064401 | Method to Control the Common Drain of a Pair of Control Gates and to Improve Inter-Layer Dielectric (ILD) Filling Between the Control Gates - A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided. | 03-03-2016 |
20160064656 | Phase Change Memory Structure to Reduce Leakage from the Heating Element to the Surrounding Material - A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell. | 03-03-2016 |
20160086965 | Self-Aligned Split Gate Flash Memory - The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced. | 03-24-2016 |
20160087056 | SPLIT GATE MEMORY DEVICE FOR IMPROVED ERASE SPEED - Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device. | 03-24-2016 |
Shih-Chang Liu, Kaoshiung County TW
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20120056305 | SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width. | 03-08-2012 |
Shih-Chang Liu US
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20100171167 | Gated Semiconductor Device and Method of Fabricating Same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 07-08-2010 |
Shih-Chang Shei, Tainan City TW
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20110228415 | HIGH-REFLECTION MULTILAYER COATING - A high-reflection multilayer coating, which includes a baseplate, a reflecting layer and a composite reflecting layer, in which the reflecting layer is contiguously disposed between the baseplate and the composite reflecting layer, and the composite reflecting layer is provided with a first structure layer and a second structure layer. Moreover, the first structure is mutually contiguously disposed on the reflecting layer. Accordingly, the present invention is able to achieve 95˜100% high light reflectivity over a wavelength range of 400˜800 nanometers, thus increasing light reflectivity and extending the range of reflection. The present invention is able to increase the degree of illumination, brightness and uniformity when used in various types of lamps. | 09-22-2011 |
20120305942 | EPITAXIAL SUBSTRATE, LIGHT-EMITTING DIODE, AND METHODS FOR MAKING THE EPITAXIAL SUBSTRATE AND THE LIGHT-EMITTING DIODE - An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of a light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed. | 12-06-2012 |
20120305948 | LIGHT-EMITTING DIODE AND METHOD FOR MAKING THE SAME - A light-emitting diode includes: an epitaxial substrate including a base member, and a plurality of spaced apart first light-transmissive members; a light-emitting unit including a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer; and an electrode unit electrically connected to the light-emitting unit. The first-type semiconductor layer has a bottom film covering the first light-transmissive members, a plurality of spaced apart second light-transmissive members formed on a top face of the bottom film, and a top film formed on the bottom film to cover the second light-transmissive members. | 12-06-2012 |
20130001614 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A light-emitting diode device includes: a substrate including first and second conductors; a light-emitting diode die including first and second polarity sides, and a surrounding surface formed between the first and second polarity sides; an insulator disposed around the surrounding surface; a transparent conductive layer extending from the second polarity side of the light-emitting diode die oppositely of the substrate, along an outer surface of the insulator, and to the second conductor; and a reflecting cup formed on the substrate to define a space with the substrate. The light-emitting diode die, the insulator and the transparent conductive layer are disposed in the space. | 01-03-2013 |
20130001630 | LIGHT-EMITTING DIODE STRUCTURE - A light-emitting diode structure includes first and second conductors, and a light-emitting diode unit. The light-emitting diode unit includes: a light-emitting diode die including first and second polarity sides, and a surrounding surface, the first polarity side being electrically connected to the first conductor; an insulator disposed around the surrounding surface; and a transparent conductive film extending from the second polarity side, along an outer surface of the insulator, and to the second conductor, so that the second polarity side is electrically connected to the second conductor through the transparent conductive film. | 01-03-2013 |
20130001636 | LIGHT-EMITTING DIODE AND METHOD FOR FORMING THE SAME - A light-emitting diode includes: an epitaxial substrate; a light-emitting unit including a lower semiconductor layer, and at least two epitaxial units that are separately formed on the lower semiconductor layer, the epitaxial units cooperating with the lower semiconductor layer to define two light-emitting sources that are capable of emitting different colors of light; and an electrode unit including a first electrode which is formed on an exposed portion of the lower semiconductor layer exposed from the epitaxial units, and at least two second electrodes each of which is formed on a corresponding one of the epitaxial units. A method for forming a light-emitting diode is also disclosed. | 01-03-2013 |
20130005060 | Methods for Pattering an Epitaxial Substrate and Forming a Light-Emitting Diode with Nano-Patterns - A method for patterning an epitaxial substrate with nano-patterns, includes: forming a plurality of zinc oxide nano-particles on an epitaxial substrate; dry-etching the epitaxial substrate exposed from the zinc oxide nano-particles to form nano-patterns corresponding to the zinc oxide nano-particles; and removing the zinc oxide nano-particles on the epitaxial substrate. A method for forming a light-emitting diode having a patterned epitaxial substrate with the nano-patterns is also disclosed. | 01-03-2013 |
20130025497 | NANOINK FOR FORMING ABSORBER LAYER OF THIN FILM SOLAR CELL AND METHOD OF PRODUCING THE SAME - A nanoink composition for forming an absorber layer of a thin film solar cell comprises particles and a volatile chelating agent mixing with the particles. The particles contain one or more elements selected from group IB and/or IIB and/or IVA and/or VIA. In the present invention, the volatile chelating agent is a polyetheramine which can alternatively be monoamine compounds, diamine compounds and triamine compounds and has a molecular weight of from about 100 to about 4,000. Accordingly, the particles can be reacted mutually into a single composition while the existence of the volatile chelating agent. | 01-31-2013 |
20130255535 | CZTSe NANOINK COMPOSITION AND SPUTTERING TARGET THEREOF - The present invention provides a Cu | 10-03-2013 |
20140117398 | Epitaxial Substrate, Light-Emitting Diode, and Methods for Making the Epitaxial Substrate and the Light-Emitting Diode - An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed. | 05-01-2014 |
Shih-Chang Shei, Zhudong Town TW
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20140091330 | LED PACKAGE STRUCTURE WITH TRANSPARENT ELECTRODES - The present invention discloses a LED package structure with transparent electrodes. The electrode layers | 04-03-2014 |
20140183444 | HIGH-VOLTAGE FLIP-CHIP LED STRUCTURE AND MANUFACTURING METHOD THEREOF - A high-voltage flip-chip LED structure and a manufacturing method thereof are disclosed. The manufacturing method includes: providing a die substrate, depositing a first passivation layer, forming a co-electrical-connecting layer, depositing a second passivation layer, depositing a mirror layer, forming two conductive tunnels by etching, and providing two connecting metal layers. The die substrate includes a sapphire substrate and multiple LED chips thereon. The fully transparent co-electrical-connecting layer, formed after formation of the first passivation layer, electrically connects the LED chips in series. The outer surface of the deposited second passivation layer is a flat passivation surface that enables the mirror layer thereon to be level and reflect light without optical path difference. The two connecting metal layers are provided for electrical conduction. The high-voltage flip-chip LED structure thus formed has fully transparent electrodes and can output light without optical path difference. | 07-03-2014 |
Shih-Chang Shei, Taipei TW
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20100059733 | LED Structure - An LED structure includes a first substrate; an adhering layer formed on the first substrate; first ohmic contact layers formed on the adhering layer; epi-layers formed on the first ohmic contact layers; a first isolation layer covering the first ohmic contact layers and the epi-layers at exposed surfaces thereof; and first electrically conducting plates and second electrically conducting plates, both formed in the first isolation layer and electrically connected to the first ohmic contact layers and the epi-layers, respectively. The first trenches or the second trenches allow the LED structure to facilitate complex serial/parallel connection so as to achieve easy and various applications of the LED structure in the form of single structures under a high-voltage environment. | 03-11-2010 |
Shih-Chang Su, Hukou Township, Hsinchu County TW
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20130286976 | SYSTEMS AND METHODS FOR PROVIDING CATEGORIZED CHANNEL RESERVATION - A wireless communications system and method configured to operate and communicate with a plurality of wireless communications stations in compliance with a wireless communications protocol, wherein said communications comprise transmitting a first control packet to disable at least one of the wireless communications stations from data transmissions in compliance with the wireless communications protocol, and transmit a second control packet to enable at least one of the disabled wireless communications stations to perform the data transmissions. The first control packet is transmitted using a first configuration, and the second control packet is transmitted using a second configuration. | 10-31-2013 |
Shih-Chang Su, Hukou Township TW
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20120207101 | Systems and Methods for Providing Categorized Channel Reservation - A wireless communications system for categorized channel reservation is provided with a first wireless communications module and a second wireless communications module. The first wireless communications module transmits or receives a plurality of first wireless signals. The second wireless communications module transmits a first control packet according to an activity schedule of the first wireless communications module to disable a plurality of wireless communications stations from data transmissions, and transmit a second control packet to enable a predetermined number of the wireless communications stations to perform the data transmissions. | 08-16-2012 |
20150139167 | SYSTEMS AND METHODS FOR PROVIDING CATEGORIZED CHANNEL RESERVATION - A wireless communications system and associated method are disclosed. The system, in one configuration, includes an antenna and a wireless communications module configured to operate and communicate with a plurality of wireless communications stations via the antenna, in compliance with a wireless communications protocol. The communications include transmitting a first control packet to disable at least one of the wireless communications stations from data transmissions in compliance with the wireless communications protocol. The system is also configured to transmit a second control packet to enable at least one of the disabled wireless communications stations to perform the data transmissions. The first control packet is transmitted using a first configuration transmission power or modulation scheme, and the second control packet is transmitted using a second configuration transmission power and modulation scheme. | 05-21-2015 |
20150181469 | METHODS FOR MANAGING RADIO RESOURCES BETWEEN MULTIPLE RADIO MODULES AND COMMUNICATIONS APPARATUS UTILIZING THE SAME - Communications apparatus includes first and second radio modules and an antenna array coupled to the first and the second radio modules and includes multiple antennas. When the first and the second radio modules operate at the same time, the first radio module negotiates with a first communications device an amount of antenna(s) to be used by a first message, so that the first radio module operates with the amount of the antenna(s) and second radio module operates with at least one of the remaining antenna(s). | 06-25-2015 |
Shih-Chang Tsai, Hsinchu TW
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20080286884 | METHOD FOR IN-SITU REPAIRING PLASMA DAMAGE AND METHOD FOR FABRICATING TRANSISTOR DEVICE - A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process containing plasma to remove a portion of the substrate. The soft plasma etching process is less than 30% of the power used in the main etching process. | 11-20-2008 |
20080305635 | METHOD FOR FABRICATING A PATTERN - A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask. | 12-11-2008 |
20100209675 | ETCHING METHOD - The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer having a first hard mask layer and a second hard mask layer successively formed thereon and then patterning the second hard mask layer. Thereafter, an etching process is performed to pattern the first hard mask layer by using the patterned second hard mask layer as a mask, and the etching process is performed with a power of about 1000 W. Next, the material layer is patterned by using the patterned first hard mask layer as a mask. | 08-19-2010 |
20160086806 | Method for Disconnecting Polysilicon Stringers During Plasma Etching - A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles. | 03-24-2016 |
Shih-Chang Tsai, Tainan City TW
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20160093712 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a first dielectric layer thereon. The first dielectric layer is provided with a trench. Then, a metal layer is formed to fill the trench and to cover the surface of the first dielectric layer. The metal layer is partially removed so that a remaining portion of the metal layer covers the first dielectric layer. A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion. A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench. | 03-31-2016 |
Shih-Chang Wang, Hsinchu City TW
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20100252453 | CONTROL SOLUTION FOR DETERMINING PERFORMANCE OF ELECTROCHEMICAL SENSING SYSTEM AND METHOD FOR THE SAME - A control solution for determining the performance of an electrochemical sensing system for measuring the concentration of an analyte in a body fluid sample and methods using the same are provided. The control solution contains the analyte at a predetermined amount and an alcohol-containing adjustor. The control solution generates a current signal from the electrochemical sensing system when the performance of the electrochemical sensing system is qualified and obtains a measured concentration corresponding to the current signal, wherein the measured concentration is less than the real concentration corresponding to the predetermined amount. | 10-07-2010 |
Shih-Chang Wu, Hsinchu Hsiang TW
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20110128028 | PROBE CARD, MAINTENANCE APPARATUS AND METHOD FOR THE SAME - A maintenance apparatus and a maintenance method for a probe card are provided. The maintenance apparatus includes a first supporting member, a second supporting member, a first clamping member, a second clamping member, and a plurality of locking units. In the maintenance method, the first supporting member and the second supporting member are initially positioned underneath below the two sides of a positioning slice, respectively, and then the first clamping member and the second clamping member are each disposed on the first supporting member and the second supporting member, respectively. First clamping member and first supporting member, and second clamping member and second supporting member are secured together respectively by locking units. Thus two sides of positioning slice are secured tightly and the positioning slice is well fastened. A probe card is also provided. The probe card includes a guide slot having a size corresponding to that of maintenance apparatus. | 06-02-2011 |