Patent application number | Description | Published |
20080230834 | Semiconductor apparatus having lateral type MIS transistor - A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor. | 09-25-2008 |
20090233565 | Receiving decive - A receiving device is provided capable of avoiding reception of unnecessary energy when a signal waveform actually changes on a receiving side. An impedance control circuit includes a sensing unit to sense one or more of a voltage, current, or power of a signal to be received by a receiving circuit. The impedance control unit varies an input impedance according to the change in the sensed one or more quantities so that the received signal will be reflected. Thus the excess energy of the signal is reflected and fed to any other receiving circuit achieving stable communications. | 09-17-2009 |
20090296830 | SIGNAL RECEIVER FOR RECEIVING DIFFERENTIAL SIGNAL VIA TRANSMISSION LINE - A signal receiver includes: a receiving circuit that receives a differential signal via a transmission line, which includes a pair of signal wires for transmitting the differential signal; and an impedance control circuit that controls an input impedance so as to reduce a common mode noise. The impedance control circuit includes a detection element for detecting at least one of a voltage, a current and an electric power of the common mode noise. The impedance control circuit controls the input impedance in accordance with change of the at least one of the voltages the current and the electric power of the common mode noise. | 12-03-2009 |
20100102857 | Switching circuit and driving circuit for transistor - A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector. | 04-29-2010 |
20100177829 | Receiving device including impedance control circuit and semiconductor device including impedance control circuit - A receiving device includes a receiving circuit and an impedance control circuit. The receiving circuit receives a signal transmitted through a communication line. The impedance control circuit is coupled with the receiving circuit and has a detecting part. The detecting part detects a physical value of the signal and the physical value includes at least one of a voltage, an electric current, and an electric power. The impedance control circuit changes an input impedance based on the detected value so that a ringing of the signal is reduced. | 07-15-2010 |
20110073904 | Semiconductor device having SOI substrate and method for manufacturing the same - A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element. | 03-31-2011 |
20110084730 | TRANSMISSION APPARATUS FOR DIFFERENTIAL COMMUNICATION - A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and a power line or a ground line. Each noise protection circuit is provided to a corresponding transmission lines. Each noise protection circuit includes a ground potential detector and an impedance controller. The ground potential detector detects a potential of the corresponding transmission line with respect to the ground line. The impedance controller causes an impedance of the corresponding transmission line with respect to the ground line to become equal to an impedance of the other transmission line with respect to the ground line, when the detected potential becomes outside a predetermined potential range. | 04-14-2011 |
20110135014 | Transmission device for differential communication - In a transmission device for differential communication, a first cathode-side element part is coupled between a first communication line and a cathode-side power supply line, a second cathode-side element part is coupled between a second communication line and the cathode-side power supply line, a first anode-side element part is coupled between the first communication line and an anode-side power supply line, and a second anode-side element part is coupled between the second communication line and the anode-side power supply line. A driving portion drives the element parts based on transmission data input from an outside. A target potential generating portion generates target potentials of the element parts based on potentials of the first communication line and the second communication line. | 06-09-2011 |
20110210766 | DRIVING CIRCUIT FOR TRANSISTOR - A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector. | 09-01-2011 |
20110291157 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer. | 12-01-2011 |
20110298446 | CURRENT SENSOR, INVERTER CIRCUIT, AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell. | 12-08-2011 |
20120061726 | LATERAL INSULATED-GATE BIPOLAR TRANSISTOR - A N-channel lateral insulated-gate bipolar transistor includes a semiconductor substrate, a drift layer, a collector region, a channel layer, an emitter region, a gate insulation film, a gate electrode, a collector electrode, an emitter electrode. The collector region includes a high impurity concentration region having a high impurity concentration and a low impurity concentration region having a lower impurity concentration than the high impurity concentration region. The collector electrode is in ohmic contact with the high impurity concentration region and in schottky contact with the low impurity concentration region. | 03-15-2012 |
20120139079 | DIODE - A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface. | 06-07-2012 |
20120182051 | DRIVING CIRCUIT FOR TRANSISTOR - A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector. | 07-19-2012 |
20130075877 | SEMICONDUCTOR DEVICE HAVING LATERAL ELEMENT - A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×10 | 03-28-2013 |
20130168730 | SEMICONDUCTOR DEVICE HAVING LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes. | 07-04-2013 |
20140048911 | LATERAL SEMICONDUCTOR DEVICE - A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other. | 02-20-2014 |
20140070271 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer. | 03-13-2014 |
Patent application number | Description | Published |
20100078763 | RESISTANCE-CHANGE MEMORY HAVING RESISTANCE-CHANGE ELEMENT AND MANUFACTURING METHOD THEREOF - A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer. | 04-01-2010 |
20100097846 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an etching rate lower than an etching rate of each of the magnetic layers. | 04-22-2010 |
20100102407 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %. | 04-29-2010 |
20100197044 | METHOD OF MANUFACTURING A MAGNETIC RANDOM ACCESS MEMORY, METHOD OF MANUFACTURING AN EMBEDDED MEMORY, AND TEMPLATE - A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern. | 08-05-2010 |
20120074511 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region. | 03-29-2012 |
20120230091 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes at least one memory cell including a magnetoresistive element, and first and second electrodes. The element includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a third magnetic layer provided on the second magnetic layer and having a magnetization antiparallel to the magnetization direction of the second magnetic layer. A diameter of an upper surface of the first magnetic layer is smaller than that of a lower surface of the tunnel barrier layer. A diameter of a lower surface of the second magnetic layer is not more than that of an upper surface of the tunnel barrier layer. | 09-13-2012 |
20120244639 | METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning. | 09-27-2012 |
20120244640 | METHOD OF MANUFACTURING MULTILAYER FILM - According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer. | 09-27-2012 |
20130248355 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT - According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first magnetic layer, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, forming a hard mask layer on the second magnetic layer, and patterning the second magnetic layer, the tunnel barrier layer, and the first magnetic layer, with a cluster ion beam using the hard mask layer as a mask, wherein the cluster ion beam comprises cluster ions, cluster sizes of the cluster ions are distributed, and a peak value of the distribution of the cluster sizes is 2 pieces or more and 1000 pieces or less. | 09-26-2013 |
20140206106 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region. | 07-24-2014 |
Patent application number | Description | Published |
20130322816 | SPOT SIZE CONVERTER AND METHOD FOR MAKING THE SAME - In order to provide a spot size converter and a method for making the same which enable the optical connection with low loss and are able to reduce the excess loss for the position misalignment in mounting, a spot size converter according to an exemplary aspect of the present invention includes: a substrate on which an optical waveguide including a first core is laminated and which includes a notch; a core reducing part which is formed so that a cross-section area of the first core may gradually decrease toward an end part of the first core in the direction of light propagation; a second core which surrounds the core reducing part and is made of a material whose refractive index is smaller than that of the first core; a peripheral clad which surrounds the second core and is made of a material whose refractive index is smaller than that of the second core; and a lower clad which is formed in a lower part of the second core and includes the peripheral clad; wherein the lower clad is formed in the notch. | 12-05-2013 |
20140105544 | OPTICAL WAVEGUIDE TYPE OPTICAL TERMINATOR - An optical waveguide type optical terminator forms an optical waveguide structure including at least an optical absorption core ( | 04-17-2014 |
20140286606 | HIGH-ORDER MODE FILTER - A high-order mode filter includes a slab region, a band-shaped projection elongated in an optical waveguide direction, a first optical waveguide including a disturbance element and a second optical waveguide. The disturbance element is formed by doping impurities into the slab region, thus indicating a lower refractive index than the slab region. Both the first optical waveguide and the second optical waveguide are alternately arranged. The first optical waveguide may include a disturbance element positioned close to the projection, while the second optical waveguide may include a disturbance element distanced from the projection in the slab region. The high-order mode filter causes a large high-order mode loss due to interference between a removable high-order mode and an intentional high-order mode at the connecting face between the first optical waveguide and the second optical waveguide, thus reducing reflected light and stray light. | 09-25-2014 |
20150049978 | SILICON-BASED ELECTRO-OPTICAL DEVICE - In a region in which silicon semiconductor layers having first and second conductive types are stacked, a concavoconvex structure including a Si | 02-19-2015 |
20150253471 | HIGH-ORDER MODE FILTER - A rib waveguide type high-order mode filter includes a plate-like slab region | 09-10-2015 |
20150277159 | OPTICAL MODULATOR AND OPTICAL MODULATION DEVICE - An optical modulator includes a plurality of electrode pads arranged in a zigzag alignment; two arms which are partially bent to circumvent the electrode pads so as to carry out optical phase modulation at various parts based on voltages input via the electrode pads; an optical branch structure branching the arms; and an optical coupling structure aggregating the arms together. Each arm is made of a silicon-base electro-optic element including a substrate; a first conductive semiconductor layer having a rib waveguide structure; a dielectric layer deposited on the rib waveguide structure; and a second conductive semiconductor layer deposited on the dielectric layer. The first conductive semiconductor layer is connected to first electrode wires via first contacts, while the second conductive semiconductor layer is connected to second electrode wires via second contacts. Thus, it is possible to miniaturize the optical modulator which can operate at a low voltage. | 10-01-2015 |
20150280832 | OPTICAL MODULATOR AND OPERATING POINT CONTROL METHOD - An optical modulator includes an optical phase modulator which applies an operating voltage to at least one arm so as to modulate an optical phase of an optical signal transmitted via at least one arm and an optical phase adjuster which applies a voltage below the operating voltage to at least one arm so as to adjust an operating point. In the optical phase adjuster, an optical phase coarse adjuster applies a voltage below the operating voltage to at least one arm so as to change an optical phase of an optical signal by 180° or more, while an optical phase fine adjuster applies a voltage below the operating voltage to at least one arm so as to changer an optical phase of an optical signal by 90° or less. Thus, it is possible to automatically calibrate an operating point of an optical modulator with low power consumption. | 10-01-2015 |
20160041338 | OPTICAL END COUPLING TYPE SILICON OPTICAL INTEGRATED CIRCUIT - An optical end coupling type silicon optical integrated circuit is provided using an SOI substrate. This optical integrated circuit is constituted so as to connect with an external optical circuit at an end coupling part and have signal light incident to an optical circuit that includes a curved part. In the plane of the optical integrated circuit, the position of one end coupling part selected from among any thereof and the position of any multimode optical waveguide element to which a respective optical waveguide is connected via a respective curved part satisfy a positional relationship defined on the basis of a beam divergence angle [theta] of stray light. | 02-11-2016 |