Patent application number | Description | Published |
20100170788 | ELECTROSENSING ANTIBODY-PROBE DETECTION AND MEASUREMENT SENSOR USING CONDUCTIVITY PROMOTION BUFFER - A sensor system for electrosensing an antigen in a test sample is disclosed. The sensor system has two electrodes electrically disconnected and physically separated from each other, and a layer of antibody is immobilized on the surface of the electrodes. The antibody has specific binding reactivity with the antigen. Conductivity promotion molecules suspended in a buffer solution may be distributed over and/or between the antibody-populated electrodes for improving electrical conductivity characteristics across the two electrodes. The antibody captures the antigen present in the test sample mixed in the buffer solution that comes into contact with the antibody-populated electrodes. This alters the electrical conductivity characteristic across the two electrodes in which an amount representative of the altering provides an indication for electrosensing of the antigen. | 07-08-2010 |
20100170792 | ELECTROSENSING ANTIBODY-PROBE DETECTION AND MEASUREMENT SENSOR - A sensor for electrosensing an antigen in a test sample is disclosed. The sensor has two electrodes electrically disconnected and physically separated from each other, and a layer of antibody is immobilized on the surface of at least one of the electrodes. The antibody has specific binding reactivity with the antigen. Conductivity promotion molecules may be tethered over and/or distributed between the antibody-populated electrodes for improving electrical conductivity characteristics across the two electrodes. The antibody captures the antigen present in the test sample mixed in a buffer solution that comes into contact with the antibody-populated electrodes. This alters the electrical conductivity characteristic across the two electrodes in which an amount representative of the altering provides an indication for electrosensing of the antigen. | 07-08-2010 |
20100171487 | ELECTROSENSING ANTIBODY-PROBE DETECTION AND MEASUREMENT METHOD - A method of electrosensing an antigen in a test sample using a sensor is disclosed. The sensor has two electrodes electrically disconnected and physically separated from each other and a layer of antibody immobilized on the surface of at least one of the electrodes. The antibody has specific binding reactivity with the antigen. The method comprises tethering conductivity promotion molecules over and/or distributing between the antibody-populated electrodes for improving electrical conductivity characteristics across the two electrodes, and measuring electrically across the electrodes after the test sample comes into contact with the antibody-populated electrodes. The antibody captures the antigen present in the test sample thereby altering the improved electrical conductivity characteristic across the two electrodes in which an amount representative of the altering providing an indication for electrosensing of the antigen. | 07-08-2010 |
20100172800 | ELECTROSENSING ANTIBODY-PROBE DETECTION AND MEASUREMENT SENSOR HAVING CONDUCTIVITY PROMOTION MOLECULES - A sensor for electrosensing an antigen in a test sample is disclosed. The sensor has two electrodes electrically disconnected and physically separated from each other, a layer of antibody immobilized on the surface of at least one of said electrodes. The antibody has specific binding reactivity with the antigen. Conductivity promotion molecules are conjugated with the antibody to improve electrical conductivity characteristics across the two electrodes. The antibody captures the antigen present in the test sample mixed in a buffer solution that comes into contact with the antibody-populated electrodes. This alters the electrical conductivity characteristic across the two electrodes in which an amount representative of the altering provides an indication for electrosensing of the antigen. | 07-08-2010 |
Patent application number | Description | Published |
20100048880 | Starch Binding Domain and Use Thereof - The present invention relates to a starch binding domain, a recombinant protein and a complex thereof. The present invention also relates to a method for separating a recombinant protein comprising a starch binding domain of the present invention. | 02-25-2010 |
20100099855 | RECOMBINANT PROTEIN COMPRISING STARCH BINDING DOMAIN AND USE THEREOF - A recombinant protein is prepared comprising a polypeptide of interest and a starch binding domain (SBD). The said SBD is obtainable from glucoamylase of fungi genus | 04-22-2010 |
20100210865 | Compounds isolated from antrodia cinnamomea and use thereof - The present invention relates to novel compounds from | 08-19-2010 |
20100286227 | Compounds from Mycelium of Antrodia Cinnamomea and Use Thereof - The present invention relates to compounds from mycelium of | 11-11-2010 |
20100324309 | Novel Mixture and Compounds from Mycelia of Antrodia Camphorata and Use Thereof - The present invention relates to a compound derived from mycelium of | 12-23-2010 |
20110201666 | COMPOUNDS FROM MYCELIUM OF ANTRODIA CINNAMOMEA AND USE THEREOF - The present invention relates to compounds from mycelium of | 08-18-2011 |
20120225492 | Starch Binding Domain and Use Thereof - The present invention provides a method for identifying starch binding sites of starch binding domain in CBM family. The CBM family is consisting of CBM20, CBM21, CBM25, CBM26, CBM34, and CBM41. The method further comprises predicting starch binding sites of starch binding domain in CBM family using the identified starch binding sites of starch binding domain with same topology. | 09-06-2012 |
20130034877 | METHOD FOR INCREASING THERMAL STABILITY AND RETAINING ACTIVITY OF A PROTEIN - The present invention provides a method and a system for increasing thermal stability of a starch binding protein (SBP)-tagged recombinant protein. The present invention also provides a method for preventing releasing a SBP-tagged recombinant protein from a SBP-binding matrix and retaining an activity of the recombinant protein in aquatic environment. | 02-07-2013 |
20130096323 | NOVEL MIXTURE AND COMPOUNDS FROM MYCELIA OF ANTRODIA CAMPHORATA AND USE THEREOF - The present invention relates to a compound derived from mycelium of | 04-18-2013 |
20130129772 | AMELIORATIVE OR PREVENTIVE EFFECT OF ANTRODIA CINNAMOMEA IN ARTHRITIS, CARTILAGE DESTRUCTION, OR CHONDROCYTE DEATH - The present invention relates to a method of preventing or ameliorating the symptoms of arthritis or preventing or ameliorating cartilage destruction or chondrocyte death in a subject suffered from arthritis, comprising administrating the subject an effective amount of an active component selected from a compound, a mixture, and a mycelium prepared from | 05-23-2013 |
20130225649 | COMPOUNDS FROM ANTRODIA CINNAMOMEA AND USE THEREOF - The present invention relates to compounds from | 08-29-2013 |
20140179753 | COMPOUNDS FROM ANTRODIA CINNAMOMEA AND USE THEREOF - The present invention relates to compounds from | 06-26-2014 |
20140343250 | RECOMBINANT BACTERIA RECOGNIZING PROTEIN AND USES THEREOF - The present invention relates to a recombinant protein comprising SEQ ID NO: 1 and a bacteria recognizing lectin. The present invention also relates to uses of the recombinant protein comprising detecting pathogens, removing endotoxins, determining the presence of an endotoxin or endotoxin-like material, and determining the presence of pathogen-associated molecular pattern (PAMP) comprising rhamnose-rhamnose (Rha-Rha), rhamnose-N-acetyl-mannosamine (Rha-ManNAc), N-acetyl-mannosamine-rhamnose (ManNAc-Rha), rhamnose-galatose (Rha-Gal), or galatose-rhamnose (Gal-Rha) in a sample, and use as a medicament, a disinfectant, a decontaminant, a surfactant or a diagnostic means. The present invention further relates to a method for prevention and/or treatment of conditions related to pathogen related infections in a patient in need thereof comprising: administering to said patient a pharmaceutically effective amount of composition comprising the recombinant protein, wherein the recombinant protein functions as an antagonist of PAMP comprising Rha-Rha, Rha-ManNAc, ManNAc-Rha, Rha-Gal, or Gal-Rha. | 11-20-2014 |
Patent application number | Description | Published |
20090059781 | METHOD AND APPARATUS FOR ICI CANCELLATION IN COMMUNICATION SYSTEMS - An apparatus capable of inter-carrier interference (ICI) cancellation in a communication system, the apparatus comprising a detecting module configured to detect an ISI-free region free from inter-symbol interference (ISI) in a guard interval (GI) of a symbol in time domain, a windowing module configured to provide a windowing function in time domain, identifying a weight value in the windowing function based on the ISI-free region, and multiplying a channel response related to the symbol by the windowing function in time domain to obtain a windowing result, wherein the windowing result comprises a first portion corresponding to the ISI-free region and a second region corresponding to an end portion of the symbol, the end portion and the ISI-free region having the same length, and a combination module configured to combine the first portion and the second portion of the windowing result in time domain. | 03-05-2009 |
20090135977 | DEVICE FOR AND METHOD OF SIGNAL SYNCHRONIZATION IN A COMMUNICATION SYSTEM - A device for signal synchronization in a communication system, the device comprising a first detector configured to perform a first sliding correlation for a received signal and a pseudo-random noise (PN) sequence to obtain information on symbol timing, a second detector configured to identify a fractional carrier frequency offset (FCFO) using the information on symbol timing and the cyclic extension property of the PN guard interval (GI), a first multiplier configured to provide a first product by multiplying the received signal with the FCFO, and a third detector comprising a set of second multipliers configured to provide a set of second products by multiplying the first product with each of a set of phases related to integral carrier frequency offsets (ICFOs), a set of sliding correlators each being configured to perform a second sliding correlation for the PN sequence and one of the set of the second products, the set of sliding correlators providing a set of peak values, and a peak detector configured to identify an ICFO by detecting an index number of a maximal value among the set of peak values. | 05-28-2009 |
20090257515 | TRANSMISSION METHOD OF WIRELESS SIGNAL AND TRANSMITTER USING THE SAME - A transmission method of a wireless signal including the following steps is provided. Multiple orthogonal frequency division multiplexing (OFDM) symbols carried by multiple subcarriers are generated according to a data signal. A scrambling pattern including multiple scrambling symbols is generated, wherein the scrambling symbols respectively correspond to the subcarriers in the frequency domain. The scrambling symbols corresponding to two contiguous subcarriers are correlated. The scrambling symbols are utilized to encode the OFDM symbols carried by the corresponding subcarriers. | 10-15-2009 |
20110150153 | Apparatus and Method for Inter-Carrier Interference Cancellation - A method for inter-carrier interference cancellation is provided. A time-domain received signal is detected to obtain information of an inter-symbol interference free region. Multiple cyclic useful symbols are obtained from the time-domain received signal according to the information of the inter-symbol interference free region and a set of multi-step windowing coefficients is generated. Adjusted cyclic useful symbols are obtained by multiplying the cyclic useful symbols by the set of multi-step windowing coefficients, respectively, and then combined in a time domain to obtain a time-domain combination signal. The inter-carrier interference of each of sub-carriers of the time-domain combination signal is centralized on neighboring D sub-carriers. The time-domain combination signal is transformed into a frequency-domain received signal. The frequency-domain received signal and its corresponding channel response matrix are divided into overlapped signal blocks according to D. Successive inter-carrier interference cancellation is performed on each signal block in parallel to obtain estimation data. | 06-23-2011 |
20120121002 | Receiver and Signal Receiving Method Thereof - A signal receiving method of a receiver includes following steps. Multiple time-domain received signals are transformed into multiple frequency-domain received signals, and channel response matrices corresponding to the frequency-domain received signals are estimated. The frequency-domain received signals are STBC decoded and multiple original combination signals are obtained based on the corresponding channel response matrices. The frequency-domain received signals are rearranged, and the rearranged frequency-domain received signals are STBC decoded and multiple rearrangement combination signals are obtained based on the corresponding channel response matrices. The original combination signals and the rearrangement combination signals are randomly chosen and summed to obtain multiple complex signals. The complex signal with minimum interference power is selected and then the selected signal is used to cancel interference and compensate the channel effect to obtain the detected data. | 05-17-2012 |
20130170539 | COMMUNICATION DEVICE CAPABLE OF CHANNEL ESTIMATION AND METHOD THEREOF - Communication methods and communication devices are disclosed. The communication method, performed by a communication device, including: receiving a time-domain OFDM symbol; converting the time-domain OFDM symbol to a frequency-domain OFDM symbol containing a plurality of pilot sub-carrier received signals; extracting the plurality of pilot sub-carrier received signals from the frequency-domain OFDM symbol; estimating a plurality of first frequency-domain channel average responses (CARs) of pilot sub-carriers according to the plurality of pilot sub-carrier received signals and a plurality of pilot sub-carrier transmitted signals; determining a pilot sub-carrier number parameter for a sub-carrier block according to a statistical information of channel delay; splitting all sub-carriers into a plurality of sub-carrier blocks according to the pilot sub-carrier number parameter; and estimating second frequency-domain CARs of all sub-carriers by performing weighting average and interpolation based on the first frequency-domain CARs of the pilot sub-carriers in all sub-carrier blocks. | 07-04-2013 |
20140003371 | TRANSMITTER AND RECEIVER AND IDENTIFICATION PATTERN TRANSMISSION METHOD AND IDENTIFICATION PATTERN DETECTION METHOD | 01-02-2014 |
Patent application number | Description | Published |
20110196635 | CONTACTLESS SENSING DEVICE - A contactless sensing device comprises a magnetic stripe fixed on a tested object, a detector and a processor. The magnetic stripe has arranged plurality of N-pole and S-pole blocks. The detector includes a fixed magnetic layer with fixed magnetic direction, a free magnetic layer with changeable magnetic direction influenced by external magnetic field, and an insulating layer separated the fixed magnetic layer from the free magnetic layer. While the object is moving to make the magnetic stripe pass through the detector, the magnetic direction of the free magnetic layer is influenced by the N-pole and S-pole blocks, such that the magnetic direction of the free magnetic layer is parallel or anti-parallel to the fixed magnetic layer. The induced change of the magnetoresistance further result in the obvious change of the output signal to the processor, and then the information of the object is sensed and calculated from the processor. | 08-11-2011 |
20120059604 | CONTACTLESS VIBRATION METER - A contactless vibration meter having a magnetic strip, a detector, and a processor is disclosed. The N-pole blocks of the magnetic strip are unequal lengths and the S-pole blocks of the magnetic strip are also unequal lengths, the detector is detecting the N-pole blocks of the magnetic strip with unequal lengths and the S-pole blocks of the magnetic strip with unequal lengths, and the voltage variation due to the change of the magnetoresistance of the detector is calculated by the processor, so as to transfer to corresponding vibrating waveform, thereby being capable of obtaining the vibrating information of the tested object. It is not limited by the space of the factory or the pattern of the tested object, and capable of being attached to detect immediately. | 03-08-2012 |
Patent application number | Description | Published |
20090057957 | APPARATUS FOR MAKING MAGNESIUM-BASED CARBON NANOTUBE COMPOSITE MATERIAL AND METHOD FOR MAKING THE SAME - An apparatus for fabrication of a magnesium-based carbon nanotube composite material, the apparatus includes a thixomolding machine, and a feeding device. The thixomolding machine includes a heating barrel, a feeding inlet, a nozzle, a heating portion, and a plunger. The heating barrel includes a first end and a second end. The feeding inlet is disposed at the first end. The nozzle is disposed at the second end. The heating portion is disposed around the heating barrel. The plunger is disposed at a center of the heating barrel. The feeding device includes a hopper; an aspirator connected to the hopper, a first container, and a second container. The hopper is in communication with the first container and the second container. A method for fabricating a magnesium-based carbon nanotube composite material is also provided. | 03-05-2009 |
20090061211 | MAGNESIUM-BASED COMPOSITE MATERIAL AND METHOD FOR MAKING THE SAME - The present invention relates to a magnesium-based composite material includes at least two magnesium-based metallic layers; and at least one magnesium-based composite layer respectively sandwiched by the at least two magnesium-based metallic layers. The present invention also relates to a method for fabricating a magnesium-based composite material, the method includes the steps of: (a) providing at least two magnesium-based plates; (b) providing a plurality of nanoscale reinforcements; (c) sandwiching the nanoscale reinforcements between the at least two magnesium-based plates to form a preform; and (d) hot pressing the preform to achieve the magnesium-based composite material. | 03-05-2009 |
20090081408 | MAGNESIUM-BASED COMPOSITE MATERIAL AND METHOD FOR MAKING THE SAME - The present invention relates to a magnesium-based composite material includes a magnesium-based metallic material, and at least one nanoscale reinforcement film disposed therein. The present invention also relates to a method for fabricating the above-described a magnesium-based composite material, the method includes the steps of: (a) providing at least two magnesium-based plates; (b) providing at least one nanoscale reinforcement film; (c) sandwiching the at least one nanoscale reinforcement film between the at least two magnesium-based plates to form a preform; and (d) hot rolling the preform to achieve the magnesium-based composite material. | 03-26-2009 |
20090127743 | METHOD FOR MAKING MAGNESIUM-BASED CARBON NANOTUBE COMPOSITE MATERIAL - A method for fabricating a magnesium-based composite material, the method includes the steps of: (a) providing a magnesium-based melt and a plurality of carbon nanotubes, mixing the carbon nanotubes with the magnesium-based melt to achieve a mixture; (b) injecting the mixture into at least one mold to achieve a preform; and (c) extruding the preform to achieve the magnesium-based carbon nanotube composite material. | 05-21-2009 |
20090146098 | POWDER EXTINGUISHING AGENT AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a powder extinguishing agent used for extinguishing fires of burning light metals. The powder extinguishing agent includes: potassium chloride in an amount from 40% to 50% by weight, sodium chloride in an amount from 45% to 55% by weight, and calcium fluoride in an amount from 2% to 8% by weight. The present invention also relates to a method for manufacturing the powder extinguishing agent. | 06-11-2009 |
20100200125 | METHOD FOR MAKING MAGNESIUM-BASED COMPOSITE MATERIAL - The present disclosure relates to a method for fabricating the above-described a magnesium-based composite material. The method includes providing at least two magnesium-based plates, providing at least one nanoscale reinforcement film, sandwiching the at least one nanoscale reinforcement film between the at least two magnesium-based plates to form a preform, and hot rolling the preform to achieve the magnesium-based composite material. | 08-12-2010 |
Patent application number | Description | Published |
20090306912 | METHOD OF MEASURING LED JUNCTION TEMPERATURE - A method of measuring LED junction temperature includes the steps of: (a) obtaining a temperature curve of an LED; (b) inputting at least one rated AC voltage to the LED; (c) measuring a temperature at a specific point on an outer packaging structure of the LED, putting the temperature measured at the specific point into the temperature curve, and calculating a junction temperature of the LED by interpolation; and (d) substituting the result from the calculation in the step (c) into a numerical analysis model to obtain temperature oscillation of the LED. | 12-10-2009 |
20130146912 | ELECTRONIC DEVICE - An electronic device including an insulating substrate, a plurality of conductive vias and a chip is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The conductive vias pass through the insulating substrate. The chip is disposed on the upper surface of the insulating substrate and includes a chip substrate, a semiconductor layer and a plurality of contacts. The semiconductor layer is located between the chip substrate and the contacts. The contacts are electrically connected to the conductive vias. The material of the insulating substrate and the material of the chip substrate are the same. | 06-13-2013 |
20130146913 | ELECTRONIC DEVICE - An electronic device including an insulating substrate, a chip and a patterned conductive layer is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The chip is disposed above the upper surface of the insulating substrate. The patterned conductive layer is disposed between the upper surface of the insulating substrate and the chip. The chip is electrically connected to an external circuit via the patterned conductive layer. Heat generated by the chip is transferred to external surroundings via the patterned conductive layer and the insulating substrate. | 06-13-2013 |
20130148344 | LIGHT EMITTING DEVICE - A light emitting device including an insulating substrate, a plurality of light emitting diode (LED) chips and a patterned conductive layer is provided. The insulating substrate has an upper surface. The LED chips are disposed on the insulating substrate and located on the upper surface. The dominant wavelengths of the LED chips are in a wavelength range of a specific color light and the dominant wavelengths of at least two of the LED chips are different. The patterned conductive layer is disposed between the insulating substrate and LED chips, and electrically connected to the LEDs chip. | 06-13-2013 |
20130240932 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device and a manufacturing method thereof are provided, wherein the semiconductor light-emitting device includes a substrate, a first type doped semiconductor layer, a light-emitting layer, a second type doped semiconductor layer and an optical micro-structure layer. The first type doped semiconductor layer is disposed on the substrate and includes a base portion and a mesa portion. The base portion has a top surface, and the mesa portion is disposed on the top surface of the base portion. The light-emitting layer is disposed on the first type doped semiconductor layer. The second type doped semiconductor layer is disposed on the light-emitting layer. The optical micro-structure layer is embedded in the first type doped semiconductor layer. | 09-19-2013 |
20140084191 | DETECTION APPARATUS - A detection apparatus comprising a chuck, a probe device, a light-sensing device and a light-concentrating unit is disclosed. The chuck bears light-emitting diode chips. The probe device includes two probes and a power supply. The end point of the probes respectively electrically connects with one of the light-emitting diode chips and the power supply to make the light-emitting diode chip emits a plurality of light beams. The light-sensing device is disposed on one side of a light-emitting surface of the light-emitting diode chip so as to receive the light beams emitted by the light-emitting diode chip. The light-concentrating unit is disposed between the light-emitting diode chip and the light-sensing device to concentrate the light beams emitted by the light-emitting diode chip. | 03-27-2014 |
20140084931 | DETECTION APPARATUS FOR LIGHT-EMITTING DIODE CHIPS - A detection apparatus for light-emitting diode chips comprises a transparent chuck with the light-concentration capability, a probing device and a light-sensing device. The transparent chuck comprises a light-incident plane and a light-emitting plane. The light-incident plane is used to bear a plurality of light-emitting diode chips under detection. The probing device comprises two probe pins and a power supply. The two ends of each probe pin is electrically connected to one of the light-emitting diode chips and the power supply, respectively, to make the light-emitting diode chip emit a plurality of light beams. The light beams penetrate through the transparent chuck by emitting into the incident plane of the transparent chuck. The light-sensing device is disposed on one side of the light-emitting plane of the transparent chuck to receive the light beams which penetrate through the transparent chuck. | 03-27-2014 |
20140159732 | DETECTION APPARATUS FOR LIGHT-EMITTING DIODE CHIP - A detection apparatus for light-emitting diode chip comprising a substrate with the function of photoelectric conversion and a probing device is disclosed. The substrate is designed to bear at least one light-emitting diode chip. The probing device comprises a power supply and at least two conductive elements. The two ends of the conductive elements are respectively electrically connected to the light-emitting diode chip and the power supply to enable the light-emitting diode chip to emit light beams. Some of the light beams are emitted from the light-emitting diode chip toward the substrate such that the light beams emitted by the light-emitting diode chip are converted into an electric signal by the substrate. | 06-12-2014 |
20140159733 | DETECTION APPARATUS FOR LIGHT-EMITTING DIODE CHIP - A detection apparatus for light-emitting diode chip comprising a light-collecting apparatus having an opening, a bracing component and a probing device is disclosed. The bracing component is designed to bear at least one light-emitting diode chip. The probing device comprises a power supply and at least two flexible current-transporting elements. The two ends of the current-transporting elements are respectively electrically connected to the light-emitting diode chip and the power supply to enable the light-emitting diode chip to emit light beams. Besides, the detection apparatus for light-emitting diode chip of the present invention further comprises a thimble to push the light-emitting diode chip into the inside of the light-collecting apparatus via the opening such that the light beams emitted by the light-emitting diode chip are collected by the light-collecting apparatus. | 06-12-2014 |
20140166716 | SPLITTING APPARATUS - A splitting apparatus suitable to split a work piece along at least one cutting line formed on the work piece is provided. The splitting apparatus includes a chopper, a detector, a controller and an adjustor. The chopper is disposed above the work piece. The detector is disposed above the work piece for transmitting a signal to the work piece so as to get a specification data of the work piece. The controller connects the detector and receives the specification data and generates an adjustment data. The adjustor connects the controller and the chopper. The adjustor receives the adjustment data and adjusts a parameter data of the chopper according to the adjustment data so that the chopper splits the work piece for once along the cutting line formed on the work piece. | 06-19-2014 |
20140170936 | WORKING MACHINE - A working machine includes a work piece, at least one signal generator and a detector. The signal generator is disposed beside the work piece for transmitting a signal. The detector is disposed beside the work piece so as to detect the signal transmitted by the signal generator and get a location information of the work piece. | 06-19-2014 |
20140252118 | SPRAY COATING APPARATUS - A spray coating apparatus including a containing tank, a spray nozzle, and a detection unit is provided. The containing tank contains a glue. The spray nozzle is connected to the containing tank to spray and coat the glue on a work piece. The detection unit detects specification data of the glue on the work piece. | 09-11-2014 |
20140268637 | WAVELENGTH CONVERTING STRUCTURE AND MANUFACTURING METHOD THEREOF - A wavelength converting structure suitable for covering a carrier carrying at least one light-emitting diode (LED) chip is provided. The wavelength converting structure includes a base film and a fluorescent layer. The base film has a first bending portion and a first flat portion connected to the first bending portion. The first flat portion is disposed on the carrier, and an accommodating space is defined by the first bending portion and the carrier. The LED chip is disposed in the accommodating space. The fluorescent layer is disposed on the base film and has a second bending portion and a second flat portion connected to the second bending portion. The second bending portion is conformal to the first bending portion, and the second flat portion is conformal to the first flat portion. | 09-18-2014 |
20150036128 | INSPECTION APPARATUS - An inspection apparatus is capable of inspecting a light-emitting diode (LED). The inspection apparatus includes a reflecting cover, a base plate, a light-collecting unit and at least one inspection light source. An enclosed space is defined by the base plate and the reflecting cover having an opening. The LED is disposed on the base plate and located in the enclosed space. The light-collecting unit is disposed above the LED and in the enclosed space. A vertical distance from the light-collecting unit to the LED is H, a width of the opening of the reflecting cover is W, and H/W=0.05 to 10. The inspection light source is in the enclosed space. An inspection light emitted from the inspection light source is reflected by the reflecting cover and then emitted into the LED. | 02-05-2015 |
Patent application number | Description | Published |
20090090929 | LIGHT-EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) chip includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and a groove. The first semiconductor layer, active layer and second semiconductor layer are formed on the substrate in sequence. The groove is formed in the first semiconductor layer, the active layer and the second semiconductor layer. | 04-09-2009 |
20110061398 | MAGNETIC REFRIGERATOR - A magnetic refrigerator has reciprocated and rotated motions. The body of the apparatus has a nearly tubular shape and contains working pieces at corners, wherein the working pieces surround a shaft with permanent magnet. Compared with existing rotational models, the magnetic refrigerator of the present invention has a relative smaller volume, and the motion of the shaft will be back and forth. Furthermore, a torque eliminating device of the magnetic refrigerator will eliminate the reverse torque when the shaft is driven reverse so that improve cooling efficiency. | 03-17-2011 |
20110067415 | MAGNETIC COMPONENT COMPILING STRUCTURE AND MAGNETIC REFRIGERATOR ADAPTING MAGNETIC COMPONENT COMPILING STRUCTURE THEREOF - A magnetic component compiling structure and a magnetic refrigerator adapts the magnetic component compiling structure thereof. The magnetic component compiling structure has more refrigerating beds and less permanent magnet per volume. Hence, the magnetic refrigerator saves more costs during manufacturing, and achieves higher cooling efficiency. | 03-24-2011 |
Patent application number | Description | Published |
20100065121 | PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element comprises a solar-energy epitaxial layer, a bond layer and a LED epitaxial layer, which are stacked sequentially. The bond layer has a plurality of holes allowing light to pass. The solar-energy epitaxial layer receives light via the holes and generates electric energy, and an external secondary battery stores the electric energy. When environmental illumination disappears, the LED epitaxial layer is powered by the external secondary battery to emit light. When the photoelectric conversion element of the present invention applies to outdoor traffic signs, advertisement signboards and indicators, they can operate without external power supply. | 03-18-2010 |
20100072487 | LIGHT EMITTING DIODE, PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED), a fabricating method thereof, and a package structure thereof are provided. The LED includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, a current distribution modifying pattern, a first electrode and a second electrode. The active layer and the second semiconductor layer form a mesa structure and expose a part of the first semiconductor layer. The current distribution modifying pattern is disposed on the second semiconductor layer. The first electrode is disposed on and electrically connected to the first semiconductor layer exposed by the mesa structure. The second electrode is disposed on the current distribution modifying pattern and is electrically connected to the second semiconductor layer. The LED has superior light emitting efficiency. | 03-25-2010 |
20130175674 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 10 | 07-11-2013 |
20130178046 | METHOD OF MANUFACTURING A SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 10 | 07-11-2013 |
20130221321 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode (LED) device includes a first LED, a second LED, and a superlattice structure by which the first and the second LEDs are stacked. The superlattice structure has an absorption spectra, the first active layer of the first LED has a first emission spectra, and the second active layer of the second LED has a second emission spectra. The absorption spectra is located on a shorter-wavelength side of at least one of the first and the second emission spectra. | 08-29-2013 |
20130285076 | LIGHT EMITTING DIODE DEVICE - A light emitting diode (LED) device includes at least one stacking LED unit. The stacking LED unit includes a plurality of epitaxial structures interleaved with tunnel junctions. For a given predetermined input power, the plurality of epitaxial structures may reduce an operating current density of the stacking LED unit as compared to an LED unit with a single epitaxial structure and the same horizontal size. The reduced operating current density approaches a quantum efficiency peak. Additionally, for a given predetermined input power, the stacking LED unit may operate in a current density interval corresponding to a quantum efficiency within 20% decrement of the quantum efficiency peak. | 10-31-2013 |
20130299774 | LIGHT-EMITTING DIODE DEVICE AND A METHOD OF MANUFACTURING THE SAME - A light-emitting diode (LED) device includes at least one LED unit, each including a substrate; an electrical coupling layer deposited above the substrate; a parallel-connected epitaxial structure deposited above the electrical coupling layer; and an intermediate layer deposited between the electrical coupling layer and the parallel-connected epitaxial structure. In another embodiment, the parallel-connected epitaxial structure is deposited above a conductive layer; the electrical coupling layer is deposited above the parallel-connected epitaxial structure; and the intermediate layer is deposited between the parallel-connected epitaxial structure and the electrical coupling layer. | 11-14-2013 |
20140008613 | STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction. | 01-09-2014 |
20140054627 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a circuit board with a layout layer and a die bonding area. At least one positive endpoint, negative endpoint and function endpoint are disposed on the layout layer. At least one semiconductor light-emitting chip is disposed within the die bonding area, and is electrically coupled to the positive endpoint, the negative endpoint and the function endpoint to facilitate various connection configurations. | 02-27-2014 |
Patent application number | Description | Published |
20080197422 | Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 08-21-2008 |
20080274573 | Method of fabricating linear cascade high-speed green light emitting diode - Green light emitting diodes (LED) of gallium arsenide (GaAs) are series-connected. The series connection has a small transmission attenuation and a wide bandwidth. The GaAs LED has a big forward bias and so neither extra driving current nor complex resonant-cavity epitaxy layer is needed. Hence, the present invention has a high velocity, a high efficiency and a high power while an uneven current distribution is avoided. | 11-06-2008 |
20080299714 | Planar Combined Structure of a Bipolar Junction Transistor and N-type/P-type Metal Semiconductor Field-Effect Transistors and Method for Forming the Same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 12-04-2008 |
Patent application number | Description | Published |
20090000769 | Temperature Controlled Loadlock Chamber - A temperature controlled loadlock chamber for use in semiconductor processing is provided. The temperature controlled loadlock chamber may include one or more of an adjustable fluid pump, mass flow controller, one or more temperature sensors, and a controller. The adjustable fluid pump provides fluid having a predetermined temperature to a temperature-controlled plate. The mass flow controller provides gas flow into the chamber that may also aid in maintaining a desired temperature. Additionally, one or more temperature sensors may be combined with the adjustable fluid pump and/or the mass flow controller to provide feedback and to provide a greater control over the temperature. A controller may be added to control the adjustable fluid pump and the mass flow controller based upon temperature readings from the one or more temperature sensors. | 01-01-2009 |
20090233410 | Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices - A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation. | 09-17-2009 |
20100123219 | Heat Spreader Structures in Scribe Lines - An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge. | 05-20-2010 |
20110127648 | Heat Spreader Structures in Scribe Lines - An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge. | 06-02-2011 |
20150021710 | Methods for Forming STI Regions in Integrated Circuits - A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface. | 01-22-2015 |
Patent application number | Description | Published |
20100127745 | DOUBLE-TRIGGERED LOGIC CIRCUIT - A double-triggered logic circuit is a composite circuitry consisting of a plurality of PMOS, NMOS, inverters and a signal line. It includes an AND logic circuit and a XNOR logic circuit to generate an adjustable pulse mode to solve the problem of threshold voltage loss. | 05-27-2010 |
20100131442 | INTELLIGENT MONITORING SYSTEM - An intelligent monitoring system aims to perform object surveillance and tracking, and can quickly build accurate and reliable background data in a complex image condition to achieve desired monitoring result. Based on a dynamic background and a temporary static object and user's requirements, monitoring objects in a background module can be added or deleted to match the actual background information. The whole background data can be tracked according to characteristics of a targeted object set by users, and post-processing can be done for the tracked object, such as zooming, identifying, capturing, surveillance of behaviors, and the like. Thus whether a special attention is needed for a dynamic or static object can be notified. And an alert can be issued to relevant people for timely handling. | 05-27-2010 |
20110110591 | MULTI-POINT IMAGE LABELING METHOD - The present invention discloses a multi-point image labeling method, which labels an object pixel matrix containing image data and makes adjacent array elements with image data have an identical image label value. A multi-point label window is used to designate a non-zero temporary labeled value to store in the register according to the temporary labeled value of the adjacent array elements. Next, a label-equivalence window generates label-equivalence information according to the adjacent temporary labeled values. Next, an equivalent-substitution processing process is performed on the temporary labeled values according to the label-equivalence information to generate label-equivalence substitution information. Then, the temporary labeled values are replaced according to the label-equivalence substitution information to obtain the resultant image labeled values and complete the image labeling of the object pixel matrix. | 05-12-2011 |
20110169631 | REAL-TIME ALARM SYSTEM - A real-time alarm system comprises an image capturing element, a network transmission system, a control processing unit and a mobile device. The image capturing element is installed on different sites to generate image information. The image information is transmitted through the network transmission system with one end linking to the image capturing element. The control processing unit is linked to the network transmission system and includes a server, and contains preset information to compare with the image information to generate comparison information. The comparison information is analyzed by a preset algorithm to judge behaviors of objects in the images. The mobile device is linked to the control processing unit to receive the image information. After the control processing unit judges specific behaviors, it actively informs the mobile device to record a video for a selected duration to be seen anytime at a remote site. | 07-14-2011 |
20110254605 | HIGH SPEED DUAL MODULUS PRESCALER - A high speed dual modulus prescaler aims to be used on a frequency synthesizer of wireless communication systems to divide frequency of input signals. The high speed dual modulus prescaler includes a first D flip-flop, a second D flip-flop and a main control transistor. The main control transistor switches connection of the first D flip-flop and second D flip-flop. The main control transistor provides an OR gate state and an AND gate state to form an OR gate circuit and an AND gate circuit in the prescaler. Thereby the number of transistors in the prescaler can be reduced to increase operation speed and lower power consumption. | 10-20-2011 |
Patent application number | Description | Published |
20100200922 | Electrostatic Discharge Protection Device and Method - Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. | 08-12-2010 |
20120119354 | Protecting Flip-Chip Package using Pre-Applied Fillet - A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials. | 05-17-2012 |
20130127052 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 05-23-2013 |
20130157430 | Electrostatic Discharge Protection Device and Method - Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. | 06-20-2013 |
20140057431 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 02-27-2014 |
Patent application number | Description | Published |
20080226378 | MULTI-FUNCTION COMBINATION PEN - A combination pen includes a tubular barrel having two open ends for selectively receiving different stationery devices so that different stationery devices can be combined together with the barrel. The stationery devices received in the barrel can be replaced if desire so that any combination that is desired by a user or that is of practical use can be made with respect to different kinds of stationery devices. The stationary devices can be selectively combined together for saving of space and ease of stowage. | 09-18-2008 |
20090190992 | INK CARTRIDGE STRUCTURE FOR PENS - An ink cartridge structure includes a resilient device coupled to an ink cartridge for absorbing impact energy acting on the ink cartridge for protection of the ink cartridge. The resilient device includes a connection bar mounted to the ink cartridge and is coupled to a retention bar that is accessible by a user with a resilient element therebetween so that the resilient element provides cushioning to the ink cartridge. The connection bar is partially fit into a hollow portion of the retention bar and forms a vent hole that is in communication with the ink cartridge so that when the retention bar, under the resilient support by the resilient element, is manually moved reciprocally with respect to the connection bar, air is pumped, through the vent hole, into the ink cartridge to force the ink contained in the ink cartridge to ward a writing tip. | 07-30-2009 |
20090257813 | AUTOMATIC PENCIL - Au automatic pencil comprising an outer pencil tube, a pencil head, a clipping device, a guiding tube and a pencil lead cylinder, characterized in that a resilient element is mounted between the guiding tube and the clipping device allowing the guiding tube to reciprocate upward and downward within the stopper. The resilient element urges the guiding tube to rise upward if the pencil lead cylinder is not depressed, and to keep a distance from the pencil lead, and to allow another pencil lead to be inserted. The pencil lead cylinder can adapt a plurality of pencil lead. | 10-15-2009 |
Patent application number | Description | Published |
20080203422 | Structure of light emitting diode and method to assemble thereof - A structure of a light emitting diode is provided. The light emitting diode comprises a light emitting diode die; two conductive frames electronically and respectively connecting to the cathode and anode of the light emitting diode die, and two substrates. Each conductive frame has a fixing hole and each substrate has a protrusive pillar. The upper opening of the fixing hole is broader than the bottom opening. The protrusive pillar is inserted into the fixing hole and the shape of the protrusive pillar is deformed for fitting and binding with the fixing hole. | 08-28-2008 |
20090032822 | HIGH POWER LIGHT EMITTING DIODE - A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin. | 02-05-2009 |
20090166661 | Light-emitting diode packaging structure and module and assembling method thereof - A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion; holding the electrode leads against the metal plates respectively; and bending the clamping portion of each of the metal plates to fix the electrode leads on the metal plates. Further, a plurality of light-emitting diodes are allowed to be mounted on the metal plates to form the light-emitting diode packaging module. | 07-02-2009 |
20110198663 | STRUCTURE OF LIGHT EMITTING DIODE AND METHOD TO ASSEMBLE THEREOF - A structure of a light emitting diode is provided. In one aspect, a light emitting diode structure comprises a light emitting diode, a conductive frame, and a substrate. The conductive frame is electrically connected to the light emitting diode and has a fixing hole connecting a first side of the conductive frame and a second side of the conductive frame opposite the first side. The fixing hole has a ladder-shaped inner sidewall with a first radius of the inner sidewall adjacent the first side smaller than a second radius of the inner sidewall adjacent the second side. The substrate has a conductive pillar that is received in the fixing hole by entering the fixing hole from the first side of the conductive frame and deformed such that the conductive pillar adheres to the ladder-shaped inner sidewall of the fixing hole. | 08-18-2011 |
Patent application number | Description | Published |
20090147566 | Phase Change Memory And Control Method Thereof - A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein. | 06-11-2009 |
20090296450 | Memory And Writing Method Thereof - A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level. | 12-03-2009 |
20110317483 | Data Programming Circuits and Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data. | 12-29-2011 |
Patent application number | Description | Published |
20110122684 | VOLTAGE COMPENSATION CIRCUIT, MULTI-LEVEL MEMORY DEVICE WITH THE SAME, AND VOLTAGE COMPENSATION METHOD FOR READING THE MULTI-LEVEL MEMORY DEVICE - A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out. | 05-26-2011 |
20110270555 | PROCESS VARIATION DETECTION APPARATUS AND PROCESS VARIATION DETECTION METHOD - A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result. | 11-03-2011 |
20110280073 | NON-VOLATILE STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF - A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line. | 11-17-2011 |
20120068177 | MEASURING APPARATUS - A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat. | 03-22-2012 |
20120320658 | NONVOLATILE STATIC RANDOM ACCESS MEMORY CELL AND MEMORY CIRCUIT - A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line. | 12-20-2012 |
20130114325 | NON-VOLATILE RANDOM ACCESS MEMORY COUPLED TO A FIRST, SECOND AND THIRD VOLTAGE AND OPERATION METHOD THEREOF - A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage. | 05-09-2013 |
20130121058 | CIRCUIT AND METHOD FOR CONTROLLING WRITE TIMING OF A NON-VOLATILE MEMORY - A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching. | 05-16-2013 |
Patent application number | Description | Published |
20110079344 | METHOD FOR MAKING A THIN FILM HAVING A METALLIC PATTERN LAYER - A method for making a thin film having a metallic pattern layer includes covering a release layer on the surface of a thin film substrate to leave a blank area of a predetermined pattern in the release layer, covering a metal layer on the release layer and the blank area, covering the metal layer with an adhesive layer, adhering a substrate-based thin film to the adhesive layer, and removing the substrate-based thin film to remove the part of the metal layer outside said blank area and the release layer together with the adhesive layer and the substrate-based thin film from the thin film substrate so that a metallic pattern layer is left on the thin film substrate for RFID (radio frequency identification) system, antennas of wireless transmission system, flexible printed circuit boards or chip on film (chip on flex) applications. | 04-07-2011 |
20110079933 | IMD/IMR TRANSFER PATTERN METHOD - An IMD (in-mold decoration)/IMR (in-mold roller or in-mold release) transfer pattern method includes the steps of (a) preparing an in-mold transfer-pattern film, (b) processing the in-mold transfer-pattern film into a predetermined three-dimensional shape fitting the configuration of the desired finished product, (c) inserting the three-dimensional in-mold transfer-pattern film in an injection-molding mold for molding with a plastic material and (d) removing the molded product from the injection-molding mold after the injection-molding mold has been cooled down and then removing the thin film substrate and the release layer of the in-mold transfer-pattern film from the molded product. This method prevents the in-mold transfer-pattern film from wrinkling or cracking during injection-molding so that the finished product has a smooth perfect surface. | 04-07-2011 |
20110086168 | METHOD FOR MAKING A TRANSFER PATTERN THIN FILM - A method for making a transfer-pattern thin film includes the step of preparing a compound mixture by mixing a hard coat material (durable agent) and a release material (release agent) with a water-based, neutral or oil-based solvent, and the step of applying the compound mixture thus obtained to the surface of a thin film substrate, so that, due to the difference in specific gravity or molecule surface extension, or due to the effect of repulsive force, reaction mechanism or bonding force of physical changes and chemical actions, or of the difference in reaction rate, the hard coat substance and release substance are separated in the compound mixture to form a hard coat layer and a release layer between the thin film substrate and the hard coat layer. | 04-14-2011 |
20110251706 | IMR (IN-MOLD ROLLER OR IN-MOLD RELEASE)/IMF (IN-MOLD FORMING) MAKING METHOD USING A DIGITAL PRINTER PRINTING AND PRE-FORMING TECHNIQUE - An IMR (in-mold roller or in-mold release)/IMF (in-mold forming) making method using a digital printer printing and pre-forming technique is disclosed to employ a digital printing technique to prepare a release layer, a protective wear-resistance layer (durable layer), an ink pattern layer, a metal pattern layer and a bonding layer (adhesive layer). In-mold roller or in-mold forming film is shaped and then molded on a plastic material through an injection-molding or pressure-casting technique so that the finished product is obtained after release from the mold and removal of the outer base layer. Further, shaped in-mold decoration film is put in an injection-molding mold or pressure-casting mold for molding and then the molded product is cut into the desired shape, finishing the fabrication. Trimming process may be applied to the shaped in-mold forming film before injection molding or pressure casting. | 10-13-2011 |
20110262676 | STRUCTURE OF COMBINED METAL CASING AND PLASTIC MEMBER - A structure of combined metal casing and plastic member comprises a metal casing, a plastic member and an adhesive tape bonded between the metal casing and the plastic member. The adhesive tape is prepared by applying an adhesive bonding agent to a narrow elongated absorptive substrate by means of coating, spray-painting or printing. By means of using the adhesive tape to bond the plastic member to the metal casing, the plastic member is firmly secured to the metal casing, simplifying rapid fabrication and reducing the product manufacturing cost. | 10-27-2011 |
Patent application number | Description | Published |
20090133921 | FLEXIBLE PC BOARD MADE THROUGH A WATER CLEANING PROCESS - A flexible PC board made through a water cleaning process includes a substrate prepared from polymers or copolymers such as PET, PI, PP, PS, PMMA, PC, PU, PBT, ABS, nylon, etc. A release layer prepared from a hydrophilic material and printed on the substrate to leave a blank zone on the substrate according to a predetermined circuit pattern, and a conduction layer bonded to the blank zone to form a circuit pattern. An electroplating process may be employed to increase the thickness of the circuit pattern formed of the conduction layer. Through a water cleaning process, the release layer is removed from the substrate, and the desired flexible PC board is obtained for bonding to a member of an electronic product by means of injection or pressure casting molding. | 05-28-2009 |
20090148674 | IN MOLD FILM WITH A 2D/3D PATTERN - Both in mold film and in mold label with a 2D or 3D pattern include a base layer, which has a flat inner surface and an outer surface that can be a 2D visual surface or 3D grating surface, a pattern layer printed on the inner surface of the base layer to show a 2D or 3D pattern, a protective layer prepared from a polymer material having high temperature resistance, acid resistance and alkali resistance characteristics and printed on the pattern layer, and an adhesion layer covered on the protective layer. In an alternate form, an anti-EMI layer is sandwiched between the protective layer and the adhesion layer for electromagnetic interference protection. | 06-11-2009 |
20090162956 | LED FABRICATION METHOD EMPLOYING A WATER WASHING PROCESS - An LED fabrication method for fabricating LEDs comprises: covering all the P-contacts and N-contacts on a wafer with a hydrophilic resin mask layer, packaging the wafer with an organic or inorganic polymer compound containing a yellow fluorescent powder (or a mixture of red and green fluorescent powders), employing a water washing process to remove the hydrophilic resin mask layer so that all the P-contacts and the N-contacts are exposed to the outside, and saw-cutting the wafer into individual dies and wire-bonding the P-contact and N-contact of each die with a respective gold wire. | 06-25-2009 |
Patent application number | Description | Published |
20090251278 | Method for prohibiting a person with a facial mask to operate an automatic teller machine - A method for prohibiting a person with a facial mask to operate an automatic teller machine essentially includes the followings steps of: a) arranging a visual spectrum camera and an alarm unit approaching an automatic teller machine (ATM); b) capturing a facial picture of an experimental subject via the camera; c) judging if the picture performs generic facial features of a human face; if false, proceed Step g); d) if true, a facial temperature of the subject is detected to gain a measured temperature; e) comparing the measured temperature with a predetermined reference temperature; if the measured temperature is not within the reference temperature range, a spurious human face is determined and Step g) goes on; f) if the measured temperature is within the reference temperature range, a genuine human face is determined and the ATM is allowably operated without proceeding Step g); and g) activating the alarm unit to transmit a warning signal without operating the ATM. | 10-08-2009 |
20130032425 | BICYCLE TRANSMISSION DEVICE - The bicycle transmission device includes a hollow tube extending through the bottom bracket and two caps are connected to two ends of the hollow tube. A motor unit has two extensions and multiple fixing assemblies, wherein the extensions are positioned by the caps. The fixing assemblies fix the motor unit to the underside of the bicycle. A shaft extends through the hollow tube and a first one-way transmission device is connected to one end of the shaft. A chainwheel and a first passive wheel are connected to the other end of the transmission shaft. Two cranks are connected to two ends of the transmission shaft. A motor located in the motor unit and has a second passive wheel. The first and second passive wheels transmit energy via the belt. The present invention reduces the space required for the motor and balances the weight of the bicycle. | 02-07-2013 |
20150022025 | SMART ENERGY-SAVING POWER SOURCE CONTROL APPARATUS AND METHOD - The present invention discloses a smart energy-saving power source control apparatus and method. The apparatus includes a sensor set and a system control unit, and the system control unit includes a moving direction determination unit, a timer, a counter, a power switch system control unit. The method includes the steps of: electrically connecting the moving direction determination unit to the direction sensor set to detect and determine the moving direction and the number of persons; defining an initial value for a numeric value of the counter, and setting a set time for the timer; incrementing the numeric value of the counter by one unit if the moving direction determination unit detects the entrance of a person, and starting counting time by the timer; decrementing the numeric value of the counter by one unit if a person exits; turning off the power switch system control unit if the numeric value of the counter is equal to the initial value; turning on the power switch system control unit if the numeric value of the counter is greater than the initial value; compulsorily resetting the counter to the initial value if the time counted by the timer is equal to the set time value and turning off the power switch system control unit, and resetting the timer and stopping counting the time. The apparatus is installed in an indoor space such as a conference room, an office, a research room, a public bathroom or a pantry with one or more exits. The invention automatically controls the switch of power without requiring any manual operation, not only capable of determining whether there is people in a controlled space, but also capable of self-correcting and removing noises to achieve the smart energy-saving effect and improve the convenience and safety of use. | 01-22-2015 |
Patent application number | Description | Published |
20090066570 | DYNAMIC SPEED FINDING METHOD - A dynamic speed finding method to detect drive speed of a target, i.e., a speeding car, to serve as evidence in writing a traffic ticket is executed in the following steps: Step A: the position and speed of a speed finding object, i.e., a moving police car, are detected; Step B: the relative position and relative speed of the target are detected; Step C: the speed of the target is calculated; and Step D, the data of the speed of the target is stored. | 03-12-2009 |
20090068925 | SMART REMOTE CONTROL SYSTEM - A smart remote control system includes a remote controller and a remote control moving device. The remote controller includes a casing, a first direction finding unit, a signal transmission unit, and an operating unit that controls the advancing direction of the car. The remote control moving device includes a signal receiving unit to receive a control signal and a directional signal transmitted from the remote controller, a main control unit to receive the signal transmitted from the remote controller to control advancing speed and direction of the body, and a second direction finding unit detecting a relative direction between the remote controller and the moving device for the moving device to identify direction and move towards that direction. | 03-12-2009 |
Patent application number | Description | Published |
20080290380 | SEMICONDUCTOR DEVICE WITH RAISED SPACERS - A semiconductor device includes a substrate and a gate formed on the substrate. A gate spacer is formed next to the gate. The gate spacer has a height greater than the height of the gate. A method of forming a semiconductor device includes providing a substrate with a gate layer. A hard mask layer is formed over the gate layer, and both layers are then etched using a pattern, forming a gate and a hard mask. A spacer layer is then deposited over the substrate, gate, and hard mask. The spacer layer is etched to form a gate spacer next to the gate. The hard mask is then removed. | 11-27-2008 |
20080290412 | SUPPRESSING SHORT CHANNEL EFFECTS - An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate. | 11-27-2008 |
20100052065 | NEW METHOD FOR MECHANICAL STRESS ENHANCEMENT IN SEMICONDUCTOR DEVICES - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region. | 03-04-2010 |
20120119298 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°. | 05-17-2012 |
20130113042 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 05-09-2013 |
20130126981 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 05-23-2013 |
20140103438 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 04-17-2014 |
20150044847 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°. | 02-12-2015 |