Patent application number | Description | Published |
20100140251 | RETHERMALIZING APPARATUS - Apparatus for and methods of rethermalizing a package of refrigerated or frozen food are disclosed. In general, heating mechanisms are brought into conductive heat transfer contact with the package of food and operated for a duration of rethermalization time to rethermalize the package of food by heating the food to a rethermalized temperature, and then, if desired, to hold the rethermalized package of food at a desired holding temperature for a duration of holding time. The rethermalization time can be relatively short (e.g., thirty minutes or less), and the holding time can range from a very short period of time to a very long period of time (e.g., four, six, eight or more hours) without significant loss of food quality. Other features of the apparatus and methods are disclosed. | 06-10-2010 |
20100140252 | RETHERMALIZING APPARATUS - Apparatus for and methods of rethermalizing a package of refrigerated or frozen food are disclosed. In general, heating mechanisms are brought into conductive heat transfer contact with the package of food and operated for a duration of rethermalization time to rethermalize the package of food by heating the food to a rethermalized temperature, and then, if desired, to hold the rethermalized package of food at a desired holding temperature for a duration of holding time. The rethermalization time can be relatively short (e.g., thirty minutes or less), and the holding time can range from a very short period of time to a very long period of time (e.g., four, six, eight or more hours) without significant loss of food quality. Other features of the apparatus and methods are disclosed. | 06-10-2010 |
20100293979 | FOOD SERVING BAR - A temperature controlled food serving having at least one channel of thermally conductive material for receiving at least one food-holding pan. The at least one channel defines an elongate pan receiving cavity for placement of the at least one food-holding pan at any desired location along the cavity. A temperature control system comprises at least one heating element for heating the at least one channel to maintain food products held in the food-holding pans at a food holding temperature. The at least one channel has at least two different temperature zones along a length of the channel so that food products in different temperature zones can be held at different food holding temperatures. | 11-25-2010 |
20120085746 | Electric Broiler - A new electric broiler is disclosed. The broiler includes a housing having a cooking chamber, and a cooking surface in the housing. Upper and lower electrical heat sources are provided in the cooking chamber above and below the cooking surface. The lower heat source includes a removable heating module having an electric heating element and a quick connect/disconnect connector for quick electrical connection and disconnection of the electric heating element to and from a quick connect/disconnect connector on the housing. The broiler also includes a module holder on the housing for holding the removable heating module. The heating module is removable from the holder for quick replacement of the module. | 04-12-2012 |
20130175253 | OVEN FOR HEATING FOOD - An oven for heating food is disclosed. The oven has at least one heating compartment with a left side wall, a right side wall, a back wall, a top wall, a bottom wall, and an open front, without a door, in open communication with a surrounding environment outside the oven. Gas flow openings are provided in the left and right side walls. The oven includes a blower for blowing gas through the gas flow openings into the heating compartment, and a heater for heating gas blowing into the heating compartment through the openings. In certain embodiments, the gas flow openings are configured such that substantially all of the gas blowing into the heating compartment is directed generally away from the open front of the compartment. | 07-11-2013 |
20130177683 | RETHERMALIZING APPARATUS - Apparatus for and methods of rethermalizing a package of refrigerated or frozen food are disclosed. In general, heating mechanisms are brought into conductive heat transfer contact with the package of food and operated for a duration of rethermalization time to rethermalize the package of food by heating the food to a rethermalized temperature, and then, if desired, to hold the rethermalized package of food at a desired holding temperature for a duration of holding time. The rethermalization time can be relatively short (e.g., thirty minutes or less), and the holding time can range from a very short period of time to a very long period of time (e.g., four, six, eight or more hours) without significant loss of food quality. Other features of the apparatus and methods are disclosed. | 07-11-2013 |
20140083309 | HOLDING OVEN - Methods, ovens, and associated apparatus. Ovens and methods are adapted for maintaining the quality of a pre-cooked food product. Rapid temperature and/or relative humidity restoration may be used. Ovens may include a partition movable to vary sizes of oven cavities. Ovens may include removable interior panels. Humidification mechanisms are adapted for generating water vapor which may be used to maintain the quality of a pre-cooked food product. | 03-27-2014 |
20140116268 | OVEN FOR HEATING FOOD - An oven for heating food is disclosed. The oven has at least one heating compartment including an open front or an open top in open communication with a surrounding environment outside the oven. A food support may be provided for supporting food in the heating compartment. Gas flow openings may be provided for introducing heated gas into the heating compartment for heating the food. The gas may be heated by a heater system and blown through the gas flow openings by a blower system. Gas may be exhausted from the heating compartment via gas flow openings in the heating compartment. The oven may include oven modules. | 05-01-2014 |
20140130684 | OVEN WITH VARIOUS FEATURES, INCLUDING BOOST HEATING AND PREHEAT STATUS - A heat control for an oven permits selective overriding of a holding cycle heating recipe with a boost heating recipe to deliver a boost of heat to food held in a heating compartment. Various types of boost heating recipes may be used. A heat control for an oven graphically displays stages of completion of a preheat cycle on an operator interface. Associated ovens and methods are also disclosed. | 05-15-2014 |
20140144334 | OVEN AND APPARATUS FOR HOLDING A FOOD ITEM IN AN OVEN CAVITY - A system includes an oven and an apparatus configured for holding at least one food item and being inserted in a cavity of the oven through an open end of the cavity. A baffle provided on the oven or apparatus has a height extending between the peripheral rim and an upper wall of the oven cavity for restricting flow of gas out of the cavity from the apparatus. Various forms of baffles may be used. The baffles may have adjustable, interchangeable, fixed position, or other configurations. | 05-29-2014 |
Patent application number | Description | Published |
20080250378 | CIRCUIT EMULATION AND DEBUGGING METHOD - A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals. | 10-09-2008 |
20090287468 | EVENT-DRIVEN EMULATION SYSTEM - A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect. | 11-19-2009 |
20110251836 | CIRCUIT EMULATION SYSTEMS AND METHODS - An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources. | 10-13-2011 |
20130035925 | METHOD AND APPARATUS FOR VERSATILE CONTROLLABILITY AND OBSERVABILITY IN PROTOTYPE SYSTEM - A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation. | 02-07-2013 |
20130055177 | SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS - User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names. | 02-28-2013 |
20130117007 | METHOD AND APPARATUS FOR TURNING CUSTOM PROTOTYPE BOARDS INTO CO-SIMULATION, CO-EMULATION SYSTEMS - A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design. | 05-09-2013 |
20130227509 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards. | 08-29-2013 |
20140157215 | SYSTEM AND METHOD OF EMULATING MULTIPLE CUSTOM PROTOTYPE BOARDS - An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires. | 06-05-2014 |
20140351777 | PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS - A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file. | 11-27-2014 |
20150294055 | SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS - User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names. | 10-15-2015 |