Shayesteh
Anahita Shayesteh, San Jose, CA US
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20110145506 | Replacing Cache Lines In A Cache Memory - In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed. | 06-16-2011 |
Anahita Shayesteh, Los Altos, CA US
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20140181477 | Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor - In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed. | 06-26-2014 |
Hamid Shayesteh, Woodinville, WA US
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20140248942 | RESONANT GAMING CHIP IDENTIFICATION SYSTEM AND METHOD - A system and method for a gaming chip identification system are disclosed. Briefly described, one embodiment comprises a plurality of gaming chips, each gaming chip operable to emit a respective unique electromagnetic signature in response to incident non-optical electromagnetic radiation, a computer-readable medium that stores information indicative of the electromagnetic signatures of at least a number of the plurality of gaming chips, and a processor-based system configured to verify that the electromagnetic signature from an interrogated gaming chip in an interrogation zone is a member of the plurality of gaming chips. | 09-04-2014 |
Maryam Shayesteh, Cork IE
Patent application number | Description | Published |
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20150364561 | IMPROVED LOW RESISTANCE CONTACTS FOR SEMICONDUCTOR DEVICES - The invention provides a method of forming at least one Metal Germanide contact on a substrate for providing a semiconducting device ( | 12-17-2015 |