Patent application number | Description | Published |
20130138651 | SYSTEM AND METHOD EMPLOYING A SELF-ORGANIZING MAP LOAD FEATURE DATABASE TO IDENTIFY ELECTRIC LOAD TYPES OF DIFFERENT ELECTRIC LOADS - A method identifies electric load types of a plurality of different electric loads. The method includes providing a self-organizing map load feature database of a plurality of different electric load types and a plurality of neurons, each of the load types corresponding to a number of the neurons; employing a weight vector for each of the neurons; sensing a voltage signal and a current signal for each of the loads; determining a load feature vector including at least four different load features from the sensed voltage signal and the sensed current signal for a corresponding one of the loads; and identifying by a processor one of the load types by relating the load feature vector to the neurons of the database by identifying the weight vector of one of the neurons corresponding to the one of the load types that is a minimal distance to the load feature vector. | 05-30-2013 |
20130138661 | SYSTEM AND METHOD EMPLOYING A MINIMUM DISTANCE AND A LOAD FEATURE DATABASE TO IDENTIFY ELECTRIC LOAD TYPES OF DIFFERENT ELECTRIC LOADS - A method identifies electric load types of a plurality of different electric loads. The method includes providing a load feature database of a plurality of different electric load types, each of the different electric load types including a first load feature vector having at least four different load features; sensing a voltage signal and a current signal for each of the different electric loads; determining a second load feature vector comprising at least four different load features from the sensed voltage signal and the sensed current signal for a corresponding one of the different electric loads; and identifying by a processor one of the different electric load types by determining a minimum distance of the second load feature vector to the first load feature vector of the different electric load types of the load feature database. | 05-30-2013 |
20130138669 | SYSTEM AND METHOD EMPLOYING A HIERARCHICAL LOAD FEATURE DATABASE TO IDENTIFY ELECTRIC LOAD TYPES OF DIFFERENT ELECTRIC LOADS - A method identifies electric load types of a plurality of different electric loads. The method includes providing a hierarchical load feature database having a plurality of layers; including with each of a plurality of the layers a corresponding load feature set, the corresponding load feature set of at least one of the layers being different from the corresponding load feature set of at least another one of the layers; including with one of the layers a plurality of different electric load types; sensing a voltage signal and a current signal for each of the different electric loads; determining at least four different load features from the sensed voltage signal and the sensed current signal for a corresponding one of the different electric loads; and identifying by a processor one of the different electric load types by relating the different load features to the hierarchical load feature database. | 05-30-2013 |
20140067299 | SYSTEM AND METHOD FOR ELECTRIC LOAD IDENTIFICATION AND CLASSIFICATION EMPLOYING SUPPORT VECTOR MACHINE - A method identifies electric load types of a plurality of different electric loads. The method includes providing a support vector machine load feature database of a plurality of different electric load types; sensing a voltage signal and a current signal for each of the different electric loads; determining a load feature vector including at least six steady-state features with a processor from the sensed voltage signal and the sensed current signal; and identifying one of the different electric load types by relating the load feature vector including the at least six steady-state features to the support vector machine load feature database. | 03-06-2014 |
Patent application number | Description | Published |
20140143621 | SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN INTEGRATED CIRCUIT - An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output. | 05-22-2014 |
20140149812 | SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second switching elements configured to control selective application of a shift enable signal to respective shift enable inputs of the respective ones of the plurality of scan chains. By appropriate control of the switching elements using test data register bits or other scan chain specific control signals, one or more debug modes can be supported by the scan test circuitry of the integrated circuit. | 05-29-2014 |
20140304562 | Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads - A SCAN chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded. Test signals are sent along at least one alternative path to an alternative input/output and a test voltage is recorded. The operational voltage is compared to the test voltage to identify a combinational path fault. | 10-09-2014 |
20140365838 | INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PATHS OF A TEST CONTROL PRIMARY INPUT - An integrated circuit comprises a primary input adapted to receive a test control signal, a primary output, and logic circuits having inputs coupled to the primary input via respective fan-out paths of the primary input. The integrated circuit further includes first test circuitry configured for testing a designated portion of the integrated circuit in a first test mode of operation with the test control signal at a first logic value, and second test circuitry coupled between the inputs of the logic circuits and the primary output and configured for testing of the fan-out paths in a second test mode of operation in which the test control signal takes on both the first logic value and a second logic value associated with a functional mode of operation. The primary input, primary output, logic circuits and test circuitry may be associated with a particular circuit core of the integrated circuit. | 12-11-2014 |