Patent application number | Description | Published |
20090111219 | WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING THE SAME - A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die. | 04-30-2009 |
20090146284 | Molded Leadless Packages and Assemblies Having Stacked Molded Leadless Packages - Molded leadless packages having improved stacked structures are disclosed. An exemplary molded leadless package includes a die attaching pad, a plurality of leads spaced apart from the die attaching pad at a periphery region of the die attaching pad, a semiconductor chip on the die attaching pad, a plurality of bonding wires electrically connecting the leads to the semiconductor chip, and a sealing member fixedly enclosing the semiconductor chip and the bonding wires while partly exposing an outer surface of each of the leads. The sealing member fills gaps between the die attaching pad and the leads and includes at least one protrusion protruding downward from the die attaching pad and the leads. | 06-11-2009 |
20090174044 | Multi-chip package - A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon. | 07-09-2009 |
20090189272 | Wafer Level Chip Scale Packages Including Redistribution Substrates and Methods of Fabricating the Same - Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with a first pitch on a first surface thereof. The redistribution substrate includes a plurality of connection wires arranged with a second pitch, which is greater than the first pitch, on a first surface thereof. The redistribution substrate expands a pad pitch from the first pitch to the second pitch by electrically connecting the pads to the connection wires. | 07-30-2009 |
20090194869 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 08-06-2009 |
20090243079 | Semiconductor device package - Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane. | 10-01-2009 |
20090244848 | Power Device Substrates and Power Device Packages Including the Same - Provided are power device substrates that comprise thermally conductive plastic materials, and power device packages including the same. An exemplary power device package includes a power device substrate that comprises a thermally conductive plastic material, and has a first principal plane that provides an electrically insulating surface and a second principal plane of which at least a portion is exposed outside a molding member. The exemplary power device package further includes one or more power devices disposed on the first principal plane of the power device substrate, and a plurality of conductive members that are electrically connected to the power device(s) in order to electrically connect the power device(s) to an external circuit. | 10-01-2009 |
20100052127 | FLIP CHIP MLP WITH CONDUCTIVE INK - A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package. | 03-04-2010 |
20100140786 | SEMICONDUCTOR POWER MODULE PACKAGE HAVING EXTERNAL BONDING AREA - Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member. | 06-10-2010 |
20100203684 | SEMICONDUCTOR PACKAGE FORMED WITHIN AN ENCAPSULATION - Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns. | 08-12-2010 |
20100289137 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 11-18-2010 |
20140217572 | Heat Sink Package - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 08-07-2014 |