Patent application number | Description | Published |
20090304017 | APPARATUS AND METHOD FOR HIGH-SPEED PACKET ROUTING SYSTEM - An apparatus and method for packet routing in a high-speed packet routing system. The apparatus includes an input unit and a control unit. The input unit temporarily stores an input packet and outputs the temporarily stored input packet to an output port determined by a previous router. The control unit determines an output port of a next router for the input packet. | 12-10-2009 |
20110083134 | APPARATUS AND METHOD FOR MANAGING VIRTUAL PROCESSING UNIT - A method and apparatus for managing a virtual processor including resources for operating application through a real central processing unit, which includes determining a utilization of a plurality of real CPUs to which a plurality of virtual processors are divided to be allocated; and repartitioning the virtual processors and reallocating the repartitioned virtual processor to at least part of the real CPUs, when the utilization of any one of the real CPUs is at a threshold or less. | 04-07-2011 |
20110107344 | MULTI-CORE APPARATUS AND LOAD BALANCING METHOD THEREOF - A multi-core apparatus and method for balancing load in the multi-core apparatus. The multi-core apparatus includes a first core that sends a save request including a context of a task, when a task is switched from an active state to a sleep state, a second core that receives an execution request and executes a task corresponding to the execution request, and a load balancer that receives the save request transmitted by the first core, and sends the execution request to the second core. | 05-05-2011 |
20120060007 | TRAFFIC CONTROL METHOD AND APPARATUS OF MULTIPROCESSOR SYSTEM - A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system. | 03-08-2012 |
20120060168 | VIRTUALIZATION SYSTEM AND RESOURCE ALLOCATION METHOD THEREOF - A virtualization system for supporting at least two operating systems and resource allocation method of the virtualization system are provided. The method includes allocating resources to the operating systems, calculating, when one of the operating systems is running, workloads for each operating system, and adjusting resources allocated to the operating systems according to the calculated workloads. The present invention determines the workloads of a plurality of operating systems running in the virtualization system and allocates time resources dynamically according to the variation of the workloads. | 03-08-2012 |
20120075316 | METHOD AND APPARATUS FOR COMPILING AND EXECUTING AN APPLICATION USING VIRTUALIZATION IN A HETEROGENEOUS SYSTEM - A method and apparatus for compiling and executing an application including Central Processing Unit (CPU) source code and Graphic Processing Unit (GPU) source code. The apparatus includes a hardware device including a CPU and a GPU; a compiler that compiles the GPU source code into a GPU virtual instruction; and a hybrid virtualization block that executes an execution file by translating the GPU virtual instruction into GPU machine code. | 03-29-2012 |
20120079498 | METHOD AND APPARATUS FOR DYNAMIC RESOURCE ALLOCATION OF PROCESSING UNITS - A method and apparatus for dynamic resource allocation in a system having at least one processing unit are disclosed. The method of dynamic resource allocation includes receiving information on a task to which resources are allocated and partitioning the task into one or more task parallel units; converting the task into a task block having a polygonal shape according to expected execution times of the task parallel units and dependency between the task parallel units; allocating resources to the task block by placing the task block on a resource allocation plane having a horizontal axis of time and a vertical axis of processing units; and executing the task according to the resource allocation information. Hence, CPU resources and GPU resources in the system can be used in parallel at the same time, increasing overall system efficiency. | 03-29-2012 |
20140156251 | SIMULATION DEVICE AND SIMULATION METHOD THEREFOR - The present invention relates to a simulation method and device. According to the present invention, a simulation method using a plurality of blocks comprises: a dividing step of dividing a simulation into computation operations for performing unique operations on the blocks and communication operations for data exchanges between different blocks; a grouping step of performing a grouping between the interdependent computation and communication operations; and a simulation performing step of performing an operation included in each group using the blocks according to whether or not the level of interdependency between the computation and communication operations is resolved. | 06-05-2014 |
Patent application number | Description | Published |
20130152041 | INTEGRATED WORKFLOW VISUALIZATION AND EDITING - Integrated workflow visualization and editing is provided using a visual graphic diagramming tool and a web application platform tool to create a workflow. A visual representation of a workflow is created using the visual graphic diagramming tool. A declarative markup language file representing the workflow is provided to a web application platform tool for further modification of the workflow. The workflow is opened in the web application platform tool and desired parameters in the workflow are set. Visualization data from the graphic diagramming tool and the set parameters are bundled in a single declarative markup language file formatted for reading by both the visual graphic diagramming tool and the web application platform tool to allow manipulations and parameterization of the workflow in both the visual graphic diagramming tool and the web application platform tool. | 06-13-2013 |
20130185348 | CLIENT APPLICATION INTEGRATION FOR WORKFLOWS - A method for providing client application integration for workflow management includes receiving a verification file, accessing a file through a client application, determining, based on the verification file, whether the accessed file includes a reference to a workflow component of a workflow stored on a server, retrieving the workflow component from the server, and displaying the workflow component referenced by the accessed file via an in-line user interface of the client application, further including displaying at least one selectable workflow management option for managing the workflow component using the client application. | 07-18-2013 |
20160057033 | CLIENT APPLICATION INTEGRATION FOR WORKFLOWS - A method for providing client application integration for workflow management includes receiving a verification file, accessing a file through a client application, determining, based on the verification file, whether the accessed file includes a reference to a workflow component of a workflow stored on a server, retrieving the workflow component from the server, and displaying the workflow component referenced by the accessed file via an in-line user interface of the client application, further including displaying at least one selectable workflow management option for managing the workflow component using the client application. | 02-25-2016 |
Patent application number | Description | Published |
20120074585 | Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer - A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die. | 03-29-2012 |
20120074587 | Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level - A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die. | 03-29-2012 |
20130200528 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. | 08-08-2013 |
20130228917 | Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP) - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. | 09-05-2013 |
20140091455 | Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging - A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die. | 04-03-2014 |
20140091482 | Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP - A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. | 04-03-2014 |
20140319678 | Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier - A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV. | 10-30-2014 |
20140327107 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate - A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties. | 11-06-2014 |
20150243575 | Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) - A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. | 08-27-2015 |
20150287708 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. | 10-08-2015 |
Patent application number | Description | Published |
20090309108 | Organic light emitting diode display device and method of manufacturing the same - An OLED display device includes a plurality of pixels including sub-pixels arranged along a first direction, the sub-pixels being arranged in an order emitting red, green, and blue lights along the first direction or in a reverse order, wherein an arrangement of colors of light emitted from sub-pixels of one pixel is symmetrical to an arrangement of colors of light emitted from sub-pixels of an adjacent pixel, and wherein a light emitting layer of the sub-pixel emitting red light includes a light emitting layer emitting red light and a light emitting layer emitting green light, a light emitting layer of the sub-pixel emitting green light includes a light emitting layer emitting green light, and a light emitting layer of the sub-pixel emitting blue light includes a light emitting layer emitting blue light and a light emitting layer emitting green light. | 12-17-2009 |
20090309109 | Organic light emitting diode display device and method of manufacturing the same - An OLED display device includes a plurality of pixels including sub-pixels arranged along a first direction, the sub-pixels being arranged in an order emitting red, blue, and green lights along the first direction or in a reverse order, wherein an arrangement of colors of light emitted from sub-pixels of one pixel is symmetrical to an arrangement of colors of light emitted from sub-pixels of an adjacent pixel, and wherein a light emitting layer of the sub-pixel emitting red light includes a light emitting layer emitting red light and a light emitting layer emitting blue light, a light emitting layer of the sub-pixel emitting blue light includes a light emitting layer emitting blue light, and a light emitting layer of the sub-pixel emitting green light includes a light emitting layer emitting green light and a light emitting layer emitting blue light. | 12-17-2009 |
20100188436 | Illumination apparatus and method of driving the same - An illumination apparatus which can easily display desired color light by individually controlling light emission of at least two organic light emitting devices while reducing the operational voltage. The illumination apparatus includes: a light emitting unit includes scanning lines, data lines crossing the corresponding scanning lines, and light emitting areas connected between the scanning lines and the data lines, where the light emitting areas include a first light emitting area including at least two first organic light emitting devices emitting a first color and a second light emitting area including at least two second light emitting devices emitting a second color different from the first color; and a driving unit non-simultaneously driving the first light emitting area and the second light emitting area to emit light during a frame. The method of driving the illumination apparatus includes individually emitting light from the first and second light emitting areas by respectively applying data signals to the first and second light emitting areas via the data lines connected thereto during a frame. | 07-29-2010 |
20110175073 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device having a uniform thin film in a sub-pixel region, and a method of manufacturing the organic light emitting display device. The organic light emitting display device includes a substrate, a pixel electrode disposed on the substrate, and a pixel define layer disposed on the substrate and exposing the pixel electrode, The surface of the pixel electrode is saw toothed or rough in shape. | 07-21-2011 |
20120299472 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus includes a substrate and a sealing member that are separated from each other; a pixel electrode on the substrate; a pixel defining layer on the pixel electrode and exposing a portion of the pixel electrode; an intermediate layer including a light emitting layer on the exposed portion of the pixel electrode; a facing electrode on the pixel defining layer and the intermediate layer; and a reflection member on a surface of the sealing member facing the substrate and patterned to have an opening portion that exposes the pixel electrode, wherein the opening portion is formed such that a boundary portion of the opening portion is closer to a center of the intermediate layer than a boundary portion of the portion of the pixel electrode exposed by the pixel defining layer. | 11-29-2012 |
20130001528 | Organic Light-Emitting Diode - An organic light-emitting diode (OLED) having first, second and third sub-pixels of different colors includes: a substrate; first and second electrodes; an organic emission layer (OEL) between the electrodes including a first OEL in the first sub-pixel, a second OEL in the second sub-pixel, and a common third OEL in the first, second and third sub-pixels; a hole transport layer (HTL) between the first electrode and OEL; a hole injection layer (HIL) between the first electrode and HTL; an intermediate layer between the HTL and HIL; a first optical thickness auxiliary layer (OTAL) between the first OEL and third OEL in the first sub-pixel and including a first hole transporting compound and a cyano group-containing compound; and a second OTAL including a second hole transporting compound between the third OEL and HTL in the first sub-pixel, and between the second OEL and HTL in the second sub-pixel. | 01-03-2013 |
20140014924 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING OF THE SAME - An organic light emitting display apparatus includes: a substrate; an insulation layer on the substrate and including first regions that are arranged along a first direction and second regions that are adjacent to the first regions and are arranged along the first direction; first lines on the insulation layer to cover the first regions and including first organic light-emitting layers; and second lines on the insulation layer to cover the second regions and including second organic light-emitting layers different from the first organic light-emitting layers. A portion of the first regions and a portion of the second regions facing each other are not parallel to the first direction. | 01-16-2014 |
20140048781 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate comprising pixels, each of which comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel, and a plurality of pixel electrodes independently formed for respective sub-pixels; a first common layer commonly formed on the pixels; first lines covering first sub-pixels arranged in a first direction, wherein the first lines comprise a first organic light-emitting layer; a plurality of second lines covering second sub-pixels arranged in the first direction, wherein the second lines comprise a second organic light-emitting layer differing from the first organic light-emitting layer; a second common layer commonly formed on the plurality of pixels, wherein the second common layer comprises a third organic light-emitting layer differing from the first organic light-emitting layer and the second organic light-emitting layer; a third common layer commonly formed on the pixels; and an opposite electrode commonly formed on the pixels. | 02-20-2014 |
20140353596 | ORGANIC LIGHT-EMITTING DIODE - An organic light-emitting diode includes a first electrode and a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; a hole transport layer between the first electrode and the emission layer and includes a first hole transport layer, a second hole transport layer, and a buffer layer between the first hole transport layer and the second hole transport layer; and an electron transport layer between the emission layer and the second electrode, wherein the buffer layer and the electron transport layer each include a mixture of an electron-transporting organometallic compound and an electron-transporting organic compound. | 12-04-2014 |
20140354142 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display apparatus and a method of manufacturing the same are disclosed. The organic light emitting display apparatus includes, for example, a pixel electrode and a bus electrode spaced apart and electrically insulated from each other, a pixel defining layer exposing a part of the pixel electrode including a central part thereof and a part of the bus electrode, a first intermediate layer on a top surface of the pixel defining layer between the pixel electrode and the bus electrode, the first intermediate layer having a first opening in a part of the bus electrode to expose a part of the bus electrode, an emission layer disposed on the first intermediate layer, and an opposite electrode disposed on the emission layer to correspond to the pixel electrode and the bus electrode and contacting the bus electrode through the first opening of the first intermediate layer. | 12-04-2014 |
20140374732 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display apparatus and a method of manufacturing the same are disclosed. The organic light emitting display apparatus includes, for example, a bus electrode, an insulating layer covering the bus electrode and having a bus electrode hole exposing at least a part of the bus electrode, a pixel electrode formed on the insulating layer and electrically coupled with the bus electrode, a pixel defining layer exposing a part of the pixel electrode and a part of the bus electrode, a first intermediate layer on the pixel defining layer and the pixel electrode, the first intermediate layer having a first opening to expose the part of the bus electrode, an emission layer disposed on the first intermediate layer, and an opposite electrode to correspond to the pixel electrode and the bus electrode and contacting the bus electrode through the first opening and the bus electrode hole. | 12-25-2014 |
20150060841 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus that includes a substrate, an organic light emitting unit formed on the substrate, a reflection member disposed on a non-light emitting region of the organic light emitting unit, and a sealing member that seals the organic light emitting unit. The organic light emitting display apparatus can function as a display apparatus or a mirror. | 03-05-2015 |
20150270510 | METHODS OF MANUFACTURING DISPLAY DEVICES - A display device includes a first optical resonance layer on a substrate, a switching structure on the first optical resonance layer, a first electrode on the switching structure, a light emitting structure on the first electrode, and a second electrode on the emitting structure. The switching structure may include a switching device and an optical distance controlling insulation layer covering the switching device. A first optical resonance distance for an optical resonance of the light may be provided between an upper face of the first optical resonance layer and a bottom face of the second electrode. | 09-24-2015 |
Patent application number | Description | Published |
20100007266 | METHOD OF PREPARING FIELD ELECTRON EMITTER AND FIELD ELECTRON EMISSION DEVICE INCLUDING FIELD ELECTRON EMITTER PREPARED BY THE METHOD - A method of preparing a field electron emitter includes preparing an aqueous solution including a carbon nanotube-nucleic acid composite, preparing a substrate to receive the carbon nanotube-nucleic acid composite, and electrophoresis-depositing the carbon nanotube-nucleic acid composite onto the substrate. | 01-14-2010 |
20130109070 | TRANSFORMANT FOR ENHANCING BIOETHANOL PRODUCTION, AND METHOD FOR PRODUCING ETHANOL BY USING SAID STRAIN | 05-02-2013 |
20140057543 | AIR EXTRACTOR GRILLE - Disclosed herein is an air extractor grille. The air extractor grille includes a grille body and a grille cover. The grille body includes a plurality of openable flaps which are arranged vertically in a successive order in a vehicle body inside a rear bumper. The grille cover covers at least a portion of the grille body. The grille cover has a plurality of vent slots formed in a front surface of the grille cover and arranged vertically in a successive order as well. A block plate is bent from a lower end of each of the vent slots in such a way that the block plate protrudes outwards, thus preventing the vent slot from being directly exposed to the outside. Therefore, when the flaps open, foreign substances are prevented from directly entering the interior of the vehicle through the flaps. | 02-27-2014 |
20140179213 | CONTROL DOOR FOR AIR CONDITIONER - Disclosed herein is a control door for an air conditioner. The control door includes a door panel that includes a plurality of discharge apertures, and is located around a vent of a housing of the air conditioner and is configured to slide to close and open the vent via the discharge apertures. A take-up shaft is disposed on each of opposite sides of the vent of the housing of the air conditioner, each of opposite ends of the door panel is wound onto the take-up shaft. The control door further includes a drive part configured to transmit a rotating force to the take-up shaft, to allow the door panel to slide around the vent of the housing of the air conditioner. | 06-26-2014 |
Patent application number | Description | Published |
20100053033 | ELECTROMAGNETIC INTERFERENCE SHIELD GLASS WITH BLACKENED CONDUCTIVE PATTERN AND METHOD OF PRODUCING THE SAME - The present invention provides a method of producing an electromagnetic interference shield glass and a blackened electromagnetic interference shield glass. The method comprises (a) forming a conductive pattern on at least one side of a front side and a rear side of glass, and (b) blackening a surface of the conductive pattern by using a solution comprising a reductive metal ion. | 03-04-2010 |
20100109978 | BLACKENED ELECTROMAGNETIC INTERFERENCE SHIELD GLASS AND METHOD OF PRODUCING THE SAME - The present invention provides a method of producing an electromagnetic interference shield glass, which comprises (a) forming a conductive pattern on at least one side of a front side and a rear side of the glass by using a conductive paste comprising a colored glass frit, and (b) firing the conductive pattern to blacken the conductive pattern, and a blackened electromagnetic interference shield glass. | 05-06-2010 |
20100117504 | EMI SHIELD GLASS WITH BLACKENED CONDUCTIVE PATTERN AND A METHOD FOR PREPARATION THEREOF - The present invention provides a method of producing a blackened electromagnetic interference shielding glass, which includes (a) forming a conductive pattern on a surface of glass on which a tin (Sn) component is diffused by using a conductive paste; and (b) firing the glass on which the conductive pattern is formed, and a blackened electromagnetic interference shielding glass. | 05-13-2010 |
20110247688 | FRONT ELECTRODE FOR SOLAR CELL HAVING MINIMIZED POWER LOSS AND SOLAR CELL CONTAINING THE SAME - Disclosed herein is a front electrode for solar cells, wherein the front electrode is configured in a structure in which a pattern including a plurality of grid electrodes arranged in parallel and at least one current collection electrode intersecting the grid electrodes is formed on a semiconductor substrate, current introduced to the grid electrodes is moved to and collected in the current collection electrode, and the width of each of the grid electrodes is increased toward the current collection electrode. | 10-13-2011 |