Patent application number | Description | Published |
20080276139 | Self-Synchronizing Pseudorandom Bit Sequence Checker - Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device. | 11-06-2008 |
20090034144 | On-Chip High Frequency Power Supply Noise Sensor - The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise cars be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a matter that does not require calibration. Also, since the sensor requires only one power supply, it can he used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can he timed to detect down to whatever frequency is needed. | 02-05-2009 |
20090059627 | LINEAR VOLTAGE REGULATOR - A linear voltage regulator is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range. | 03-05-2009 |
20090059628 | METHOD FOR REGULATING A VOLTAGE USING A LINEAR VOLTAGE REGULATOR - A method for regulating a voltage using a linear voltage regulator is provided. The linear voltage regulator has a first circuit with a primary output node and a second circuit having first and second inverters electrically coupled to the primary output node. The method includes receiving a first voltage from a voltage source at the first circuit. The method further includes removing frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node utilizing the first circuit. The method further includes removing frequency components of the output voltage in a second frequency range utilizing the first and second inverters of the second circuit, the second frequency range being greater than the first frequency range. | 03-05-2009 |
20090121736 | DISPOSABLE BUILT-IN SELF-TEST DEVICES, SYSTEMS AND METHODS FOR TESTING THREE DIMENSIONAL INTEGRATED CIRCUITS - A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit. | 05-14-2009 |
20090206952 | DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS - A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator. | 08-20-2009 |
20100019744 | VARIABLE INPUT VOLTAGE REGULATOR - A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input. | 01-28-2010 |
20110019321 | LEAKAGE SENSOR AND SWITCH DEVICE FOR DEEP-TRENCH CAPACITOR ARRAY - A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process. | 01-27-2011 |
20110161682 | PROCESSOR VOLTAGE REGULATION - A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor. | 06-30-2011 |
20120084241 | PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES - Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path. | 04-05-2012 |
20120119717 | Voltage Regulator Module with Power Gating and Bypass - Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node. | 05-17-2012 |
20120140554 | COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states. | 06-07-2012 |
20130278285 | MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA - PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology; a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal. One of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered. | 10-24-2013 |
20130280828 | MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA - PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits. | 10-24-2013 |
20140063925 | PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS - Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively. | 03-06-2014 |
20140078837 | COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states. | 03-20-2014 |
20140176183 | MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA - PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology. | 06-26-2014 |