Patent application number | Description | Published |
20100109057 | Fin field effect transistor and method of fabricating the same - A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. | 05-06-2010 |
20110079857 | Semiconductor devices and methods of manufacturing the same - In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties. | 04-07-2011 |
20110124172 | METHOD OF FORMING INSULATING LAYER AND METHOD OF MANUFACTURING TRANSISTOR USING THE SAME - Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO | 05-26-2011 |
20110237037 | Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure. | 09-29-2011 |
Patent application number | Description | Published |
20100025749 | SEMICONDUCTOR DEVICE - A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer | 02-04-2010 |
20100035425 | Integrated Circuit Devices Having Partially Nitridated Sidewalls and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 02-11-2010 |
20120282769 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 11-08-2012 |
Patent application number | Description | Published |
20090002005 | Substrate Probe Card and Method for Regenerating Thereof - Provided are a substrate of a probe card for installing a plurality of probes thereon to inspect an object by contacting the probes to the object, and a method for repairing the substrate. The substrate includes main channels electrically connected to the probes; and at least one spare channel for replacing the main channels when at least one of the main channels is damaged. Therefore, when some of the main channels of the probe substrate are damaged, the damaged main channels can be repaired using the spare channels and then the probe substrate can be reused, thereby reducing costs required for unnecessary replacement. | 01-01-2009 |
20090184726 | PROBE CARD AND METHOD OF MANUFACTURING THE SAME - Provided is a probe card and method of fabricating the same. This method comprises forming soldering bumpers electrically connected to conductive patterns on a substrate, forming probes connected to the conductive patterns and supported by the soldering bumpers, and then melting the soldering bumpers to fixing the probes to the substrate. Forming the soldering bumpers includes a step of forming the soldering bumpers in the same pattern and size by means of a photolithography process. | 07-23-2009 |
20140075253 | METHOD FOR VERIFICATION OF RECONFIGURABLE PROCESSOR - A method for verifying an operation of a reconfigurable processor is provided. The method includes generating an random test program using a test description and an architecture description, executing the generated random test program in a reconfigurable processor and in a simulator, and then comparing type of output values in the execution result. | 03-13-2014 |