Patent application number | Description | Published |
20090114927 | Multi-chips with an optical interconnection unit - A multi-chip having an optical interconnection unit is provided. The multi-chip having an optical interconnection unit includes a plurality of silicon chips sequentially stacked, a plurality of optical device arrays on a side of each of the plurality of the silicon chips such that the optical device arrays correspond to each other and a wiring electrically connecting the silicon chip and the optical device array attached to a side of the silicon chip, wherein the corresponding optical device arrays forms an optical connection unit by transmitting and receiving an optical signal between the corresponding optical device arrays in different layers. Each of the optical device arrays includes at least one of a light emitting device and a light receiving device | 05-07-2009 |
20090136235 | Probe card with optical transmitting unit and memory tester having the same - Example embodiments provide a probe card having an optical transmitting unit and a memory tester having the probe card. The probe card may include a plurality of needles connected to test terminals formed in a memory, a plurality of first terminals connected to the needles, a plurality of second terminals connected to the outside and corresponding to the first terminals, and an optical transmitting unit. The optical transmitting unit may connect the first terminals and the second terminals. | 05-28-2009 |
20090175630 | Optical interconnection system for transmitting and receiving a three-level signal and method of operating the same - Provided is an optical interconnection system that transmits and receives a three-level signal. The optical interconnection system includes a first and a second optical interconnection device that transmits and receives a two-level signal, and a synthesizer that outputs a three-level signal by synthesizing signals from the first and second optical interconnection devices. The optical interconnection system may transmit and receive a three-level signal while using an optical interconnection device that interconnects a two-level signal. | 07-09-2009 |
20100194399 | MEMORY SYSTEM, MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY SYSTEM AND MEMORY TEST SYSTEM - A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device. | 08-05-2010 |
20100195420 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM - A semiconductor memory system includes a memory controller and a memory. The memory controller includes a control signal converting unit converting a control signal into a converted control signal including n sequential clock pulses and a target clock pulse activated after a time period has elapsed from a start point of the n sequential clock pulses, and output the converted clock signal, and a controller transmitting unit converting the converted control signal into an optical signal, and transmitting the optical signal to the memory. The memory includes a memory receiving unit converting the optical signal into an electrical signal, and a control signal re-converting unit detecting the time period from the electrical signal, and converting the control signal into a control signal corresponding to the time period. | 08-05-2010 |
20110038221 | SEMICONDUCTOR MEMORY DEVICES, CONTROLLERS, AND SEMICONDUCTOR MEMORY SYSTEMS - A semiconductor memory system includes a controller and a memory device that are optical-interconnected. The controller includes a control logic configured to generate a control signal for controlling the memory device and a transmitter configured to convert the control signal into an optical signal, and output the optical signal. The memory device includes a receiving unit filter configured to convert the optical signal into an electric signal, and the electric signal based on a supply voltage corresponding to a period of the optical signal or the electric signal. | 02-17-2011 |
20110069464 | Memory module, memory system having the memory module, and method for manufacturing the memory module - Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide. | 03-24-2011 |
20110133063 | Optical waveguide and coupler apparatus and method of manufacturing the same - Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die. | 06-09-2011 |
20110134679 | MEMORY MODULE HAVING OPTICAL BEAM PATH, APPARATUS INCLUDING THE MODULE, AND METHOD OF FABRICATING THE MODULE - A memory module may include at least one memory package including an optical signal input/output (I/O) unit and a first optical beam path and a printed circuit board (PCB) on which the memory package is mounted. The PCB may have a second optical beam path configured to transmit an optical signal to the optical signal I/O unit. The memory module may further include a connecting body configured to mount the memory package on the PCB and match a refractive index of the first optical beam path with a refractive index of the second optical beam path. | 06-09-2011 |
20110194803 | OPTICAL MODULATOR FORMED ON BULK-SILICON SUBSTRATE - An optical modulator comprises a bulk-silicon substrate comprising a trench having a predetermined width and a predetermined depth. A bottom cladding layer is formed in the trench, and a plurality of waveguides and a phase modulation unit are formed on the bottom cladding layer. A top cladding layer is formed on the plurality of waveguides and the phase modulation unit. | 08-11-2011 |
20110206381 | OPTICAL SERIALIZING/DESERIALIZING APPARATUS AND METHOD AND METHOD OF MANUFACTURING SAME - An optical serializer/deserializer (SERDES) includes serializing circuitry which includes a source of a plurality of unmodulated optical signals, a modulation unit for generating a plurality of modulated optical signals using a plurality of electrical signals to modulate the plurality of unmodulated optical signals, and a coupling unit for delaying the plurality of modulated optical signs to generate a plurality of delayed modulated optical signals and combines the delayed modulated optical signals to generate a serialized modulated optical signal. Deserializing circuitry of the SERDES includes an optical splitter for splitting a serialized modulated optical signal into a plurality of modulated split optical signals, a demodulation unit for demodulating the modulated split optical signals and generating a respective plurality of demodulated split optical signals, and a delay unit for delaying each of the plurality of demodulated split optical signals by a respective delay amount such that the serialized modulated optical signal is converted into a respective plurality of parallel demodulated split optical signals. | 08-25-2011 |
20110243492 | SILICON BASED OPTICAL MODULATORS AND METHODS OF FABRICATING THE SAME - A silicon based optical modulator apparatus can include a lateral slab on an optical waveguide, the lateral slab protruding beyond side walls of the optical waveguide so that a portion of the optical waveguide protrudes from the lateral slab towards a substrate. | 10-06-2011 |
20120002495 | MEMORY SYSTEM, MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY SYSTEM AND MEMORY TEST SYSTEM - A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device. | 01-05-2012 |
20120087673 | OPTICAL INTERCONNECTION SYSTEM FOR TRANSMITTING AND RECEIVING A THREE-LEVEL SIGNAL AND METHOD OF OPERATING THE SAME - Provided is an optical interconnection system that transmits and receives a three-level signal. The optical interconnection system includes a first and a second optical interconnection device that transmits and receives a two-level signal, and a synthesizer that outputs a three-level signal by synthesizing signals from the first and second optical interconnection devices. The optical interconnection system may transmit and receive a three-level signal while using an optical interconnection device that interconnects a two-level signal. | 04-12-2012 |
20130015546 | MULTI-LAYER PHOTOELECTRIC INTEGRATED CIRCUIT DEVICE WITH OVERLAPPING DEVICESAANM Joe; In-sungAACI SeoulAACO KRAAGP Joe; In-sung Seoul KRAANM Suh; Sung-dongAACI SeoulAACO KRAAGP Suh; Sung-dong Seoul KRAANM Na; Kyoung-wonAACI SeoulAACO KRAAGP Na; Kyoung-won Seoul KRAANM Ha; Kyoung-hoAACI SeoulAACO KRAAGP Ha; Kyoung-ho Seoul KRAANM Kim; Seong-guAACI Pyeongtaek-siAACO KRAAGP Kim; Seong-gu Pyeongtaek-si KRAANM Shin; Young-hwackAACI Yeonsu-guAACO KRAAGP Shin; Young-hwack Yeonsu-gu KR - An integrated circuit device includes a plurality of device layers disposed on a substrate. A first one of the device layers includes at least one photo device and/or at least one electronic device and a second one of the device layers includes at least one photo device overlying the at least one photo device and/or the at least one electronic device of the first one of the device layers. | 01-17-2013 |
20130064496 | OPTICAL LINKS, MANUFACTURING METHODS THEREOF, AND MEMORY SYSTEMS HAVING THE SAME - An optical link may include a main optical waveguide; N sub-optical waveguides, where N is a natural number; N mode couplers, each configured to perform a mode coupling operation between the main optical waveguide and a respective one of the N sub-optical waveguide; and an optical wavelength filter connected to an output terminal of the main optical waveguide and an output terminal of each of the N sub-optical waveguides. A memory system may include a memory device, a memory controller, and the optical link. A data processing system may include the memory system and a central processing unit connected to the memory system through a bus. | 03-14-2013 |
20130092980 | PHOTODETECTOR STRUCTURES INCLUDING CROSS-SECTIONAL WAVEGUIDE BOUNDARIES - A photodetector structure can include a silicon substrate and a silicon layer on the silicon substrate, that can include a first portion of an optical transmission medium that further includes a silicon cross-sectional transmission face. A germanium layer can be on the silicon substrate and can include a second portion of the optical transmission medium, adjacent to the first portion can include a germanium cross-sectional transmission face butt-coupled to the silicon cross-sectional transmission face. | 04-18-2013 |
20130343696 | OPTICAL INTEGRATED CIRCUITS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND METHODS OF MANUFACTURING THE SAME - An optical integrated circuit may include a substrate including a single crystalline semiconductor material, a passive element extending in a <100> crystal orientation of the substrate and including the single crystalline semiconductor material, and an active element extending in a <110> crystal orientation of the substrate and including the single crystalline semiconductor material. | 12-26-2013 |
20140376859 | MULTI-LAYER PHOTOELECTRIC INTEGRATED CIRCUIT DEVICE WITH OVERLAPPING DEVICES - An integrated circuit device includes a plurality of device layers disposed on a substrate. A first one of the device layers includes at least one photo device and/or at least one electronic device and a second one of the device layers includes at least one photo device overlying the at least one photo device and/or the at least one electronic device of the first one of the device layers. | 12-25-2014 |