Patent application number | Description | Published |
20110267535 | IMAGE SENSOR MODULE HAVING IMAGE SENSOR PACKAGE - An image sensor module includes a circuit board, an image sensor package and an optical system. The circuit board has an upper surface and a lower surface, the substrate having a window. The image sensor package includes a mounting substrate and an image sensor chip mounted on the mounting substrate, the image sensor package being adhered to the lower surface of the circuit board such that the image sensor chip is exposed through the window. The optical system is provided on the upper surface of the circuit board to guide light from an object to the image sensor chip. | 11-03-2011 |
20110285889 | CAMERA MODULE AND METHOD OF MANUFACTURING THE CAMERA MODULE - A camera module includes an image sensor chip including a substrate having first and second opposite surfaces and a ground pad on the first surface, a housing surrounding the sides of the image sensor chip but which leaves the second surface of the image sensor chip exposed, an electromagnetic wave-shielding film united with the housing, and an electrical conductor electrically connected to the ground pad. The camera module also has an optical unit disposed on the first surface of the image sensor chip in the housing to guide light from an object to the image sensor chip. The electrical conductor extends through a side of the housing. The conductor also contacts the electromagnetic wave-shielding film to electrically connect the ground pad and the electromagnetic wave-shielding film. | 11-24-2011 |
20130181314 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a light transmissive cover having a conductive pattern, a substrate having a cavity, a semiconductor chip in the cavity of the substrate and electrically connected to the conductive pattern arranged on the light transmissive cover, and a blocking pattern between the light transmissive cover and the substrate. | 07-18-2013 |
20140073079 | CAMERA MODULE AND METHOD OF MANUFACTURING THE CAMERA MODULE - A camera module includes an image sensor chip including a substrate having first and second opposite surfaces and a ground pad on the first surface, a housing surrounding the sides of the image sensor chip but which leaves the second surface of the image sensor chip exposed, an electromagnetic wave-shielding film united with the housing, and an electrical conductor electrically connected to the ground pad. The camera module also has an optical unit disposed on the first surface of the image sensor chip in the housing to guide light from an object to the image sensor chip. The electrical conductor extends through a side of the housing. The conductor also contacts the electromagnetic wave-shielding film to electrically connect the ground pad and the electromagnetic wave-shielding film. | 03-13-2014 |
Patent application number | Description | Published |
20120304703 | WASHING MACHINE - A washing machine having an improved structure which increases washing capacity without increasing the size of the washing machine. The washing machine includes a cabinet including an outer part and a cylindrical inner part connected to the outer part, a spin basket rotatably disposed in the inner part and including a bottom and a side wall extending from the bottom, a pulsator rotatably disposed in the spin basket, a motor provided under the spin basket, a clutch to selectively transmit power of the motor to the spin basket or the pulsator, a base plate to fix the clutch and the motor, and suspension members connecting the base plate to the upper portion of the cabinet. Wash water is stored within the spin basket and is not stored outside the spin basket during a washing cycle. | 12-06-2012 |
20130031938 | WASHING MACHINE - A washing machine capable of increasing the washing capacity without enlarging the external appearance and also discharging a washing water during a washing operation or a spin-dry operation while completely isolated from electronic parts and thus reducing the risk of a power failure and fire, the washing machine including a body, a rotating tub rotatably disposed inside the body, a pulsator rotatably disposed inside the rotating tub, a driving part provided on a lower portion of the rotating tub to selectively rotate the rotating tub and the pulsator, a base plate to which the driving part is fixed, wherein a waterproofing member is provided between the base plate and a bottom of the body to seal the driving part and to prevent water from reaching the driving part. | 02-07-2013 |
20130036776 | WASHING MACHINE - A washing machine includes a cabinet forming an external appearance of the washing machine, a rotary tub disposed to rotate around a driving shaft vertically provided inside the cabinet and including a sidewall, which extends with inclination to have a diameter increasing from a lower side to an upper side of the washing machine, and at least one protrusion part, which protrudes from the sidewall with inclination to have a diameter increasing from an upper side to a lower side of the sidewall. A guide water filter is mounted on at least one protrusion part inside the rotary tub and provided at a rear surface thereof with a drain passage to discharge the washing water discharged from the balance ring to outside. A base is installed at the lower side of the rotary tub and includes a guide part and a support plate. | 02-14-2013 |
Patent application number | Description | Published |
20100246239 | Memory device using a variable resistive element - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 09-30-2010 |
20100246247 | Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same - A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N. | 09-30-2010 |
20110107049 | METHOD AND APPARATUS ADAPTED TO PREVENT CODE DATA FROM BEING LOST IN SOLDER REFLOW - A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted. | 05-05-2011 |
20110185259 | OVERWRITABLE NONVOLATILE MEMORY DEVICE AND RELATED DATA WRITE METHOD - A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region. | 07-28-2011 |
20120113710 | NON-VOLATILE MEMORY ARRAY AND EVICE USING ERASE MARKERS - A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state. | 05-10-2012 |
20120269021 | MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 10-25-2012 |
20130308370 | MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 11-21-2013 |
Patent application number | Description | Published |
20090168493 | SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL - In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells. | 07-02-2009 |
20100118593 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM THEREOF - A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit. | 05-13-2010 |
20150026516 | AUXILIARY POWER SUPPLY AND USER DEVICE INCLUDING THE SAME - A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO). | 01-22-2015 |
Patent application number | Description | Published |
20120235279 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern. | 09-20-2012 |
20130095663 | METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE - A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer. | 04-18-2013 |
20130292847 | Semiconductor Devices and Methods of Manufacturing the Same - A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad. | 11-07-2013 |
20140054659 | SEMICONDUCTOR DEVICES AND METHODS FABRICATING SAME - Disclosed are semiconductor devices and methods of forming the same. According to the semiconductor device, gate structures are provided to be buried in a substrate and first dopant regions and second dopant regions are provided at both ends of the gate structures. Conductive lines cross the gate structures and are connected to the first dopant regions. Contact structures are respectively provided in contact holes which are provided between the conductive lines and expose the second dopant regions. The contact structures are in contact with the second dopant regions, respectively. Each of the contact structures includes a pad pattern extending along a sidewall of the contact hole. | 02-27-2014 |
20140057440 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes. | 02-27-2014 |
Patent application number | Description | Published |
20080299467 | Mask mold, manufacturing method thereof, and method for forming large-sized micro pattern using mask mold - Disclosed are a mask mold, a manufacturing method thereof, and a method for forming a large-sized micro pattern using the manufactured mask mold, in which the size of a nano-level micro pattern can be enlarged using a simple method with low cost and interference and stitching errors between cells forming a large area can be minimized. The method for manufacturing the mask mold includes the operations of coating resist on a mask or a plurality of small molds having an engraved micro pattern, pressing the small molds to imprint the micro pattern on the resist, curing the resist, and releasing the small molds from the resist. | 12-04-2008 |
20100072245 | High speed and fine substrate alignment apparatus in roll to roll system - Disclosed is a substrate alignment apparatus capable of performing coarse and fine alignments of a substrate in a progressing route to remove or reduce an alignment error between the substrate and a pattern roll. The coarse alignment may be performed by moving a frame using a stage when the alignment error is relatively large, and the fine alignment may be performed by moving subsidiary rollers of a roller unit relative to a main roller of a roller unit when the alignment error is relatively small. An example substrate alignment apparatus may include a frame and a roller unit rotatably fixed to the frame to support a substrate, wherein the roller unit includes a main roller, and at least one subsidiary roller fixed to the main roller such that the at least one subsidiary roller can move relative to the main roller to align the substrate. | 03-25-2010 |
20100140220 | Nano-imprint lithography methods - In forming a pattern on a substrate with reduced pattern error using a mold having an area smaller than an area of the substrate, a first resin pattern is formed on at least a first of a plurality of regions of an etching object layer by imprinting resin applied to the etching object layer using a first mold The etching object layer is then etched using the first resin pattern as an etching mask. A second resin pattern is formed on at least a second of the plurality of regions by imprinting resin applied to the etching object layer using a second mold. The etching object layer is again etched using the second resin pattern as an etching mask. | 06-10-2010 |
20100282162 | Roll-to-roll patterning apparatus and patterning system having the same - Disclosed herein is a roll-to-roll patterning apparatus and a patterning system using the same. The patterning system may include a supply roll to supply a film member, a recovery roll to recover the film member, and a roll-to-roll patterning apparatus forming a coating on the film member. The roll-to-roll patterning apparatus may include a pattern roller, a plurality of press rollers, and an alignment roller. The pattern roller may include an outer peripheral surface with a first pattern. The plurality of press rollers may press a film member against the pattern roller to form a second pattern on the film member. The alignment roller may be spaced apart from the pattern roller and may be arranged at an upstream position in a movement direction of the film member. The alignment roller may align the film member entering a region between the pattern roller and the plurality of press rollers. | 11-11-2010 |
20100290143 | Color filter and apparatus and method of manufacturing the same - Disclosed herein are a color filter having a black matrix and an apparatus and method of manufacturing the same. The method may include applying an organic film to a substrate, forming a pattern on the organic film by applying pressure to the organic film with a mold having prominences and depressions, and forming a black matrix by applying an ink to the pattern of the organic film. The formation of the black matrix may be achieved by a roll to roll method. The black matrix is easily formed by carrying out imprinting and printing on the organic film applied to the substrate. The black matrix may have a fine line width of a nano level by imprinting and printing. Further, since the black matrix is formed by the roll to roll method, material costs may be reduced and the color filter may be manufactured at a relatively high speed. | 11-18-2010 |
20110300345 | Surface Having Superhydrophobic Region And Superhydrophilic Region - According to an example embodiment, a patterned surface includes a micro-structural surface with a micro or nano pattern on a substrate, wherein the micro-structural surface has superhydrophobic regions and superhydrophilic regions. | 12-08-2011 |
20120125215 | Roll Printing Apparatus - According to example embodiments, a roll printing apparatus includes a cleaning device in which a cleaning nozzle unit and a spray nozzle unit are integrated so that both a reverse offset process and a cliche cleaning process may be achieved in the roll printing apparatus. The roll printing apparatus may include a base plate, a blanket roll to transfer an ink material to a cliche and a substrate, a blanket roll supporter located on the base plate to support the blanket roll, a cliche table located on the base plate to fix and move the cliche, a substrate table located on the base plate to fix the substrate, and the cleaning device installed on the base plate to clean the cliche. The cleaning device may include a cleaning nozzle unit to spray a cleaning solution and a spray nozzle unit to spray DIW, which are integrated. | 05-24-2012 |
20140154863 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming semiconductor device includes forming a landing pad, forming a stopping insulating layer on the landing pad, forming a lower molding layer including a first material on the stopping insulating layer, forming an upper molding layer including a second material different from the first material on the lower molding layer, forming a hole vertically passing through the upper molding layer and the lower molding layer and exposing the landing pad, forming a first electrode in the hole, removing the upper molding layer to expose a part of a surface of the first electrode, removing the lower molding layer to expose another part of the surface of the first electrode, forming a capacitor dielectric layer on the exposed parts of the surface of the first electrode, and forming a second electrode on the dielectric layer. | 06-05-2014 |
20140220782 | METHODS OF FORMING HOLE PATTERNS OF SEMICONDUCTOR DEVICES - A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern. | 08-07-2014 |
Patent application number | Description | Published |
20120216096 | Memory Device and Memory System - A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data. | 08-23-2012 |
20120242517 | METHODS OF COMPRESSING DATA IN STORAGE DEVICE - At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword. | 09-27-2012 |
20130268724 | SSD WITH RAID CONTROLLER AND PROGRAMMING METHOD - A solid state drive (SSD) includes non-volatile memory devices and a RAID controller. Each of the non-volatile memory devices includes a memory cell array having a plurality of physical pages. The RAID controller performs a parity operation on 1st through (N−1)th physical page data to generate Nth physical page data, determines a physical page group including 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices, respectively, such that at least two of the 1st through Nth physical pages have different bit error rates from each other, and stores the 1st through Nth physical page data in the 1st through Nth physical pages, respectively. | 10-10-2013 |
20140108362 | DATA COMPRESSION APPARATUS, DATA COMPRESSION METHOD, AND MEMORY SYSTEM INCLUDING THE DATA COMPRESSION APPARATUS - Provided are data compression method, data compression apparatus, and memory system. The data compression method includes receiving input data and generating a hash key for the input data, searching a hash table with the generated hash key, and if it is determined that the input data is a hash hit, compressing the input data using the hash table; and searching a cache memory with the input data, and if it is determined that the input data is a cache hit, compressing the input data using the cache memory. | 04-17-2014 |
20140189279 | METHOD OF COMPRESSING DATA AND DEVICE FOR PERFORMING THE SAME - A data compression method includes receiving an input data stream including a previous data block and a current data block, and executing a first comparison of a part of the previous data block with part of a previous reference data block, and a second comparison of the current data block with a current reference data block, where the first and second comparisons are executed in parallel. The method further includes selectively, based on results of the first and second comparisons, outputting the current data block or compressing an extended data block, where the extended data block includes the part of the previous data block and the current data block. | 07-03-2014 |
20140195702 | METHOD OF OPERATING DATA COMPRESSION CIRCUIT AND DEVICES TO PERFORM THE SAME - A method of operating a data compression circuit includes receiving and storing a plurality of data blocks until a cache is full and writing the data blocks that have been stored in the cache to a buffer memory when the cache is full. The method also includes performing forced literal/literal encoding on each of the data blocks regardless of repetitiveness of each data block when the cache is full. | 07-10-2014 |
Patent application number | Description | Published |
20100157702 | Semiconductor memory device adopting improved local input/output line precharging scheme - A semiconductor memory device capable of preventing or minimizing bit line disturbance and performing a low-voltage high-speed operation includes a read data path circuit including a bit line sense amplifier, a local input/output line sense amplifier, a column selecting unit to operationally connect bit lines connected to the bit line sense amplifier to local input/output lines connected to the local input/output line sense amplifier in response to a column selection signal, and a local input/output line precharging unit to precharge the pair of local input/output lines by a first precharging unit, equalizing the pair of local input/output lines by an equalizing unit, and to precharge the local input/output lines by a second precharging unit following an elapsed time after the bit line sense amplifier is activated, while the column selection is deactivated. | 06-24-2010 |
20140149808 | MEMORY DEVICES AND MEMORY SYSTEMS HAVING THE SAME - In one example embodiment, a memory device includes a cell array configured to receive data at an associated address in response to a write command. The memory device further includes a storage unit configured to receive the associated address and the data in response to the write command and output the data to the associated address of the cell array in response to a rewrite command. The memory device further includes a violation determining unit configured to determine violation data, count a number of the violation data and determine data written to the storage unit as the violation data if a storage duration of the written data is less than a write recovery time (tWR). | 05-29-2014 |
20140185395 | METHODS OF COPYING A PAGE IN A MEMORY DEVICE AND METHODS OF MANAGING PAGES IN A MEMORY SYSTEM - A method of copying a page in a memory device having a plurality of memory blocks and a plurality of sets of bit lines is disclosed, wherein each of the plurality of memory blocks includes a plurality of pages, and each set of bit lines corresponds to a respective memory block, wherein first bit lines of a source memory block that includes a source page are respectively coupled to second bit lines of a target memory block that includes a target page. The method includes disconnecting between the first bit lines of thea source memory block including a source page and from the second bit lines of a the target memory block including a target page; transferring data stored in the source page to the first bit lines of the source memory block; transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block; and writing the data transferred to the second bit lines of the target memory block into the target page. | 07-03-2014 |
20140189226 | MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A memory device includes a memory cell array, a multi-purpose register (MPR) and a control unit. The memory cell array includes a plurality of memory blocks. The multi-purpose register (MPR) stores physical address information for each of the plurality of memory blocks. The control unit outputs the physical address information stored in the multi-purpose register in response to an MPR read command received from a memory controller. | 07-03-2014 |
20140241099 | SEMICONDUCTOR MEMORY AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses. | 08-28-2014 |
20140359242 | MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE - A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device. | 12-04-2014 |
Patent application number | Description | Published |
20130021298 | DISPLAY DEVICE AND DRIVING METHOD THEREOF - A display device includes: a display panel; and a sensing signal processor connected to the display panel, in which the display panel includes: a gate line which transmits a gate signal; a sensing signal line crossing the gate line; a reference sensing signal line crossing the gate line; a sensing unit connected to the gate line and the sensing signal line, where the sensing unit senses light by a touch on the display panel; and a reference sensing unit connected to the gate line and the reference sensing signal line and blocked from the light by the touch, and where the sensing signal processor is connected to the sensing unit and the reference sensing unit and includes a comparator. | 01-24-2013 |
20130056732 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes: a substrate; an infrared sensing transistor on the substrate; a readout transistor connected to the infrared sensing transistor; a power source line; and a light blocking member on the infrared sensing transistor, where the infrared sensing transistor includes a light blocking film on the substrate, a first gate electrode contacting and overlapping the light blocking film and connected to a power source line, a first semiconductor layer on the first gate electrode overlapping the light blocking film, and first source and drain electrodes on the first semiconductor layer, where the readout transistor includes a second gate electrode on the substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and second source and drain electrodes the second semiconductor layer, and where the power source line and the first gate electrode are at a same layer. | 03-07-2013 |
20130249817 | PHOTOSENSOR, DISPLAY DEVICE INCLUDING THE SAME, AND DRIVING METHOD THEREOF - A photosensor includes a sensing switching element, a sensing element, and a reset switching element. The sensing switching element includes an output terminal connected to a sensing signal line, a control terminal connected to a first gate line, and an input terminal connected to the first node. The sensing element includes an output terminal connected to a first node, a control terminal connected a second gate line disposed next to the first gate line, and an input terminal connected to a source voltage line transmitting a source voltage. The sensing element senses light. The reset switching element includes an output terminal connected to the first node, a control terminal connected to the second gate line, and an input terminal connected to a driving voltage line transmitting a driving voltage. | 09-26-2013 |
20140002764 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME | 01-02-2014 |
20140021518 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes: a first substrate; a photo transistor on the first substrate; and a switching transistor connected to the photo transistor. The photo transistor includes a light blocking film on the first substrate, a first gate electrode on the light blocking film and in contact with the light blocking film, a first semiconductor layer on the first gate electrode and overlapping the light blocking film, and a first source electrode and a first drain electrode on the first semiconductor layer. The switching transistor includes a second gate electrode on the first substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and a second source electrode and a second drain electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are at a same layer of the display device, and each includes crystalline silicon germanium. | 01-23-2014 |
20140061681 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND ELECTRO-WETTING DISPLAY PANEL HAVING THE SAME - In a display substrate, a method for manufacturing the display substrate and an electro-wetting display apparatus including the display substrate, the display substrate includes a base substrate, a sidewall defining a unit pixel area, a pixel electrode, a hydrophobic insulating layer and a light blocking layer. The sidewall is on the base substrate and defines the unit pixel area. The pixel electrode is in the unit pixel area. The hydrophobic insulating layer is on the sidewall and the pixel electrode. The light blocking layer is on the hydrophobic insulating layer and overlaps the sidewall. | 03-06-2014 |
Patent application number | Description | Published |
20110161965 | JOB ALLOCATION METHOD AND APPARATUS FOR A MULTI-CORE PROCESSOR - A method and apparatus for performing pipeline processing in a computing system having multiple cores, are provided. To pipeline process an application in parallel and in a time-sliced fashion, the application may be divided into two or more stages and executed stage by stage. A multi-core processor including multiple cores may collect correlation information between the stages and allocate additional jobs to the cores based on the collected information. | 06-30-2011 |
20110161978 | JOB ALLOCATION METHOD AND APPARATUS FOR A MULTI-CORE SYSTEM - A method and apparatus for efficiently allocating jobs to processing cores included in a computing system, are provided. The multi-core system includes a plurality of cores that may collect performance information of each respective core while the cores are executing a requested task in parallel. The multi-core system allocates additional jobs of the requested task to the cores based on the performance information and the amount of jobs remaining. | 06-30-2011 |
20110258413 | APPARATUS AND METHOD FOR EXECUTING MEDIA PROCESSING APPLICATIONS - An apparatus and method for executing media processing applications in a heterogeneous multicore system are provided. The media processing application executing apparatus includes a configuration deciding unit to decide a configuration for a combination of computational kernels and cores in which the computation kernels are to be executed. The computation kernels are media processing components included in a media processing application. The media processing application executing apparatus also includes an execution unit including multiple heterogeneous cores, to execute the media processing application based on the determined configuration. | 10-20-2011 |
20120047513 | WORK PROCESSING APPARATUS FOR SCHEDULING WORK, CONTROL APPARATUS FOR SCHEDULING ACTIVATION, AND WORK SCHEDULING METHOD IN A SYMMETRIC MULTI-PROCESSING ENVIRONMENT - A work scheduling technology in a symmetric multi-processing (SMP) environment is provided. A work scheduling function for a SMP environment is implemented in a work processing apparatus, thereby reducing the scheduling overhead, and enhancing the efficiency in use of CPU resources and improving the CPU performance. | 02-23-2012 |
20120047514 | SCHEDULING SYSTEM AND METHOD OF EFFICIENTLY PROCESSING APPLICATIONS - A scheduling technique for use in a multicore system, which can be shared by a plurality of applications, is provided. According to the scheduling technique, it is possible to perform dependency resolving and a runnable work search in parallel with the execution of cores. | 02-23-2012 |
20120059869 | WEB BROWSING SYSTEM AND METHOD FOR RENDERING DYNAMIC RESOURCE URIS USING SCRIPT - A method of communicating with a web server for web browsing, and an apparatus and system to perform the method, is provided. The method includes extracting resource information from script included in web page information, transmitting the resource information to the web server to request a resource corresponding to the resource information, and storing the resource. | 03-08-2012 |
20120124464 | APPARATUS AND METHOD FOR EXTRACTING CASCADING STYLE SHEET RULES - Provided are an apparatus and method for extracting cascading style sheet (CSS) rules. The apparatus includes a generation unit configured to generate an identification list that includes identification symbols that correspond to one or more selectors, for each document object model (DOM) node. The apparatus also includes a rule extraction unit configured to select a target DOM node and extract one or more CSS rules that are applicable to the target DOM node based on identification symbols that are included in an identification list that corresponds to the target DOM node. | 05-17-2012 |
Patent application number | Description | Published |
20110087821 | APPARATUS TO ACCESS MULTI-BANK MEMORY - A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. | 04-14-2011 |
20110202704 | MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER - A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer. | 08-18-2011 |
20110218795 | SIMULATOR OF MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES AND METHOD OF SIMULATING MULTI-CORE SYSTEM EMPLOYING RECONFIGURABLE PROCESSOR CORES - Provided are a simulator of a multi-core system employing reconfigurable processor (RP) cores and a method of simulating a multi-core system employing RP cores. The simulator includes a structure builder to receive a structure definition file defining a structure of a system, select components described in the structure definition file from a component library, and fill a data structure with the selected components to generate a structure model of a multi-core system, and a simulation engine to execute an application program according to the structure model and output the result. | 09-08-2011 |
20110246170 | APPARATUS AND METHOD FOR SIMULATING A RECONFIGURABLE PROCESSOR - A processor simulation technique to evaluate the performance of a processor that executes application programs is provided. The processor simulation technique may be used to optimize the execution of an application program. A simulator of a reconfigurable processor including a plurality of functional units models a processor by representing routing paths between functional units that generate operands and functional units that consume the operands. The size of each queue may be decided based on information regarding routing delays between functional units and stage information of iteration loops according to modulo scheduling received from a scheduler. A modeling code DB that stores host-oriented binary codes for operations of routing queues is also provided. The simulation may be performed by executing a host-directed binary code corresponding to a binary file instead of the binary file. | 10-06-2011 |
20110252179 | APPARATUS AND METHOD FOR ROUTING DATA AMONG MULTIPLE CORES - An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information. | 10-13-2011 |
20120089808 | MULTIPROCESSOR USING A SHARED VIRTUAL MEMORY AND METHOD OF GENERATING A TRANSLATION TABLE - A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address. | 04-12-2012 |
20120092987 | ROUTING APPARATUS AND NETWORK APPARATUS - A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data. | 04-19-2012 |
20120113128 | COMPUTING APPARATUS AND METHOD USING X-Y STACK MEMORY - A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis. | 05-10-2012 |
20120124343 | APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND - Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second instruction operand, and to modify the selected first instruction operand and the selected second instruction operand to reduce the operand instructions that are input to the first selector and the second selector. | 05-17-2012 |
20120151154 | LATENCY MANAGEMENT SYSTEM AND METHOD FOR MULTIPROCESSOR SYSTEM - A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal. | 06-14-2012 |
20120158394 | SIMULATION APPARATUS AND METHOD FOR MULTICORE SYSTEM - A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules. | 06-21-2012 |
20120221797 | MULTI-PORT CACHE MEMORY APPARATUS AND METHOD - Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache. | 08-30-2012 |
20130067203 | PROCESSING DEVICE AND A SWIZZLE PATTERN GENERATOR - A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations. | 03-14-2013 |
20130089102 | COARSE-GRAINED RECONFIGURABLE ARRAY BASED ON A STATIC ROUTER - Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network. | 04-11-2013 |
20140143441 | CHIP MULTI PROCESSOR AND ROUTER FOR CHIP MULTI PROCESSOR - Provided is a chip multi processor that supports both a packet switching method and a circuit switching method, and a router for the chip multi processor. According to an aspect, the chip multi processor includes a plurality of nodes that each include a router, and a plurality of links formed between the routers. Each of the routers may transfer a first type of data based on packet switching and a second type of data based on circuit switching. | 05-22-2014 |
20140215193 | PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF - Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit. | 07-31-2014 |
20140337849 | APPARATUS AND JOB SCHEDULING METHOD THEREOF - An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance. | 11-13-2014 |
20140359335 | MULTI-CORE APPARATUS AND JOB SCHEDULING METHOD THEREOF - A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores. | 12-04-2014 |
20150084957 | METHOD AND APPARATUS FOR ROUTING DATA AND RECONFIGURING RENDERING UNIT - Provided are method and apparatuses for routing and reconfiguring rendering data, the method for routing including identifying, at a processor, a group of input data, transmitting the input data based on a routing path designated for the identified group, and updating the routing path based on a feedback signal regarding the transmitted data. The method for reconfiguring rendering units including measuring, at a processor, workloads of the rendering units used in rendering a previous frame, and reconfiguring the rendering units during rendering a current frame based on the workloads. | 03-26-2015 |
Patent application number | Description | Published |
20140092356 | CURVED DISPLAY DEVICE - A curved display device includes a bent first substrate and a bent second substrate spaced apart and facing each other, a sealant positioned at edges of the first substrate and the second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate and contained by the sealant, wherein the first substrate and the second substrate are bent to have almost the same curvature radius, and a modulus of elasticity of the sealant, at least when bending of the bent first and second substrates occurs, is about 1 MPa to about 100 MPa and more specifically about 1 MPa to about 50 MPa so that the sealant can be easily shear deformed during the bending process. | 04-03-2014 |
20140198290 | Display Device and a Method of Manufacturing the Same - The present invention relates to a display device and a method of manufacturing the display device. The display device according to an exemplary embodiment of the present invention includes a substrate. A pixel electrode is formed on the substrate. A roof layer is formed on the pixel electrode. A first micro-cavity and a second micro-cavity are disposed between the pixel electrode and the roof layer. A liquid crystal fills the first and second micro-cavities. The first and second micro-cavities are connected to each other by a path. The path penetrates the roof layer. | 07-17-2014 |
20140268000 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a substrate, a cover layer which defines a tunnel-shaped cavity on the substrate, a support part which extends from the cover layer and corresponds to an edge of the tunnel-shaped cavity, a liquid crystal layer in the tunnel-shaped cavity, first and second electrode which apply an electric field to the liquid crystal layer, and a sealant layer which seals the tunnel-shaped cavity. | 09-18-2014 |
20150036073 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a display substrate which includes a plurality of pixel areas and is curved in a first direction, an opposite substrate which faces the display substrate, is coupled to the display substrate, and is curved along the display substrate, and a liquid crystal layer disposed between the display substrate and the opposite substrate, where a plurality of domains are defined in each of the plurality of pixel areas, directions in which liquid crystal molecules of the liquid crystal layer are aligned are different from each other in at least two domains among the plurality of domains, and the plurality of domains is arranged in a second direction crossing the first direction. | 02-05-2015 |