Patent application number | Description | Published |
20100223502 | MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT - A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration. | 09-02-2010 |
20120221316 | MEMORY-BASED TRIGGER GENERATION SCHEME IN AN EMULATION ENVIRONMENT - A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration. | 08-30-2012 |
20130318484 | Third Party Component Debugging For Integrated Circuit Design - The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected. | 11-28-2013 |
20140278329 | Modeling Content-Addressable Memory For Emulation - Aspects of the invention relate to techniques for modeling content-addressable memory for emulation. An emulation device according to various embodiments of the invention comprises one or more memory modeling blocks reconfigurable to emulate a content-addressable memory or a random-access memory. The emulation device may be processor-based or FPGA-based. Each of the one or more memory modeling blocks comprises memory circuitry and a dedicated comparison unit configured to compare a search word or a portion of a search word received by the each of the one or more memory modeling blocks with data stored in the memory circuitry. The comparison unit may comprise a comparator and a register coupled to the comparator and configured to store matching data. The matching data may be unencoded matching data. A plurality of the memory modeling blocks may be programmable to emulate a single content-addressable memory. | 09-18-2014 |
Patent application number | Description | Published |
20090044157 | Acyclic Modeling of Combinational Loops - Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops. | 02-12-2009 |
20120180011 | Register Transfer Level Design Compilation Advisor - Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” a first description of a circuit design into a third description for a circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of the corresponding portion of the circuit design. For example, if the first description will be implemented on an emulator, then the elaboration may describe the primitive components that will be used for the emulation model, along with the interconnections between the primitive components. | 07-12-2012 |
20140032204 | Partitionless Multi User Support For Hardware Assisted Verification - Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process. | 01-30-2014 |
20140052430 | Partitionless Multi User Support For Hardware Assisted Verification - Embodiments of the disclosed technology are directed toward facilitating the concurrent emulation of multiple electronic designs in a single emulator without partition restrictions. In certain exemplary embodiments, an emulation environment comprising an emulator and an emulation control station is provided. The emulation control station includes a model compaction module that is configured to combine multiple design models into a combined model. In some implementations, the design models are merged to form the combined model, where each design model is represented as a virtual design with the combined model. Subsequently, the emulator can be configured to implement the combined model. Furthermore, an emulation clock control component is provided that allows for portions of the emulated combined model to be “stalled” during emulation without affecting other portions. | 02-20-2014 |
Patent application number | Description | Published |
20100097758 | FLEXIBLE AIRFLOW BAFFLE FOR AN ELECTRONIC SYSTEM - A baffle manages airflow through optionally mounted electronic components by using flexible members formed to extend to empty connectors and flex away from the connectors to accommodate electronic components mounted to the connectors. | 04-22-2010 |
20100327135 | Method And Apparatus For Engaging A Rail With Various Support Structures - An assembly for engaging a rail with support structures includes a bracket disposed at an end of the rail. The bracket is configured to rotate between at least first and second positions such that the bracket can present at least first or second different engagement features for engaging with different kinds of support structures. | 12-30-2010 |
20110043986 | POWER SUPPLY ASSEMBLY FOR SERVER RACK AND METHOD FOR MOUNTING POWER SUPPLY FOR SERVER RACK - A power supply assembly for electronic components, such as servers, can include a power supply and a mount. The power supply is connected to the mount and is configured to power a plurality of electronic components. The power supply assembly can include a connection between the power supply and mount that is configured to permit the power supply to pivot about an axis in relation to the mount. | 02-24-2011 |
20140295711 | CONNECTOR - A compression connector includes a housing and a plurality of contacts located within the housing. Each of the plurality of contacts is configured to bend at a plurality of locations when pressure is applied to the contact. In addition, each of the plurality of contacts is configured to tuck within itself when pressure is applied to the contact. Furthermore, each of the plurality of contacts is constrained by the housing. | 10-02-2014 |
Patent application number | Description | Published |
20110126110 | Systems and Algorithm For Interfacing With A Virtualized Computing Service Over A Network Using A Lightweight Client - Systems and algorithm for controlling a virtualized computer service remotely through a client includes defining a virtual infrastructure in which a plurality of virtual machines are running on a hypervisor with at least one of the virtual machine executing an image processor algorithm. The image processor algorithm is configured to receive a connection request from the client for controlling the virtualized computer service (or simply, virtual service) available at a specific virtual machine. The request includes a plurality of connection parameters that describe the connection requirements of the client and is received at the virtual machine that is equipped with the image processor algorithm. The connection parameters are interrogated using the image processor algorithm to identify a specific virtual machine that provides the requested virtualized computer service. A framebuffer data for the identified virtual machine located in virtual memory is accessed and read directly through a hypervisor. The framebuffer data is processed into a plurality of image data packets using the image processor algorithm and transmitted to the client for presenting on a display device associated with the client. The image data packet grammar is tailored to the client and represents an image of the virtual machine display for the identified virtual machine. | 05-26-2011 |
20110126198 | Methods for Interfacing with a Virtualized Computing Service over a Network using a Lightweight Client - Methods for controlling a virtualized computer service remotely through a client includes receiving a connection request from the client for controlling the virtual service available at a virtual machine. The request includes a plurality of connection parameters that describe the connection requirements of the client and is received at a virtual machine that is equipped with an image processor algorithm. The connection parameters are interrogated using the image processor algorithm to identify a specific virtual machine that provides the requested virtualized computer service. A framebuffer data for the identified virtual machine located in virtual memory is accessed and read directly through a hypervisor. The framebuffer data is processed into a plurality of image data packets using the image processor algorithm and transmitted to the client for presenting on a display device associated with the client. The image data packet grammar is tailored to the client and represents an image of the virtual machine display for the specific virtual machine. | 05-26-2011 |
20120314599 | Methods and Apparatus for Using a Layered Gear to Analyze and Manage Real-time Network Quality of Service Transmission for Mobile Devices on Public Networks - Methods and apparatus for providing layered gear mechanism to analyze network loss and latency conditions includes bundling data into data packets of varying depths, at a source with data packets of each depth belonging to a particular data type. The data packets of varying depths are transmitted in layers over a network, to a destination. Information for the transmitted data packets for each layer is collected constantly and analyzed as the data progresses along the network to identify corresponding network transmission characteristics. The transmission of subsequent data packets for anyone of the layers is adjusted based on the network transmission characteristics. The adjusting is repeated one or more times based on the analyzed information for the transmitted data packets. The transition metrics for each layer is utilized for relative analysis of transmission metrics across the layers to set the adjusting. | 12-13-2012 |
20130268580 | Systems and Algorithm For Interfacing with a Virtualized Computing Service Over a Network Using a Lightweight Client - Systems and algorithm for providing a service to a client includes defining a virtual infrastructure in which a plurality of virtual machines are running on a virtualization layer with at least one of the virtual machine executing an image processor algorithm. The image processor algorithm is configured to access framebuffer data of a specific virtual machine that includes the service to be controlled, process the framebuffer data to generate image data packets with contextual information by scanning the framebuffer data to discern the image of the virtual machine display, evaluate the framebuffer data to identify contiguous areas of activity, extract data related to the contiguous areas of activity and package the extracted data into image data packets. The image data packets are transmitted to the client for presenting on a display device of the client. | 10-10-2013 |
20130346479 | Systems and Algorithm For Interfacing with a Virtualized Computing Service Over a Network Using a Lightweight Client - Systems and algorithm for providing a service to a client includes defining a virtual infrastructure in which a plurality of virtual machines are running on a virtualization layer with at least one of the virtual machine executing an image processor algorithm. The image processor algorithm is configured to access framebuffer data of a specific virtual machine that includes the service to be controlled, process the framebuffer data to generate image data packets with contextual information by scanning the framebuffer data to discern the image of the virtual machine display, obtaining connection parameters and client characteristics of a connection to the client, analyzing the framebuffer data to balance performance of the connection and performance of the specific virtual machine, and selecting a compression technique for processing the framebuffer data to generate image data packets. The image data packets are transmitted to the client for presenting on a display device. | 12-26-2013 |
20140254376 | Methods and Apparatus for Using a Layered Gear to Analyze and Manage Real-Time Network Quality of Service Transmission for Mobile Devices on Public Networks - Methods for providing layered gear mechanism to enable optimal transmission of data packets includes identifying types of data that are scheduled for transmission over a network. Data packets are generated at different depths for a particular type of data identified for transmission, wherein the data packets are generated at a source. The data packets of different depths are transmitted in different layers over a network, to a destination, wherein each layer of data packets corresponds to a specific depth. Response for the data packets transmitted in each layer is collected from the network as the data packets progress along the network. The response is analyzed to identify network transmission characteristics for each layer. A depth is selected for transmitting subsequent data packets for the particular data type based on the network transmission characteristics obtained through the analysis. | 09-11-2014 |