Patent application number | Description | Published |
20090235108 | AUTOMATIC PROCESSOR OVERCLOCKING - Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency. | 09-17-2009 |
20110022356 | DETERMINING PERFORMANCE SENSITIVITIES OF COMPUTATIONAL UNITS - Performance sensitivities to a change in performance capabilities of computational units of a computer system are determined based on measured utilization metrics for each of the computational units. In order to determine the performance sensitivities, in one approach, the computational units are operated at a first performance level, and respective first utilization metrics are determined. The computational units are then operated at a second performance level and respective second utilization metrics are determined. The sensitivity to performance capability change, e.g., a frequency change, is determined based on the respective first and second utilization metrics. The performance sensitivities of the computational units to a change in performance capability are continually updated in response to, e.g., a process context change of a computational unit or in response to a predetermined period of time elapsing since the last sensitivity to a performance capability change was determined for a computational unit. | 01-27-2011 |
20110022833 | ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY - One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units. | 01-27-2011 |
20110022857 | THROTTLING COMPUTATIONAL UNITS ACCORDING TO PERFORMANCE SENSITIVITY - A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed. | 01-27-2011 |
20120188259 | Mechanisms for Enabling Task Scheduling - Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device. | 07-26-2012 |
20120194524 | Preemptive Context Switching - Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on a accelerated processing device. Embodiments include, detecting by an accelerated processing device a memory exception, and preempting a process from running on the accelerated processing device based upon the detected exception. | 08-02-2012 |
20120194525 | Managed Task Scheduling on a Graphics Processing Device (APD) - Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process. | 08-02-2012 |
20120194527 | Method for Preempting Graphics Tasks to Accommodate Compute Tasks in an Accelerated Processing Device (APD) - Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed. The method also includes evicting currently executing wavefronts associated with the task from being processed based upon predetermined criteria | 08-02-2012 |
20120194528 | Method and System for Context Switching - Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved. | 08-02-2012 |
20120198458 | Methods and Systems for Synchronous Operation of a Processing Device - Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device. | 08-02-2012 |
20120200576 | Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta - Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta. | 08-09-2012 |
20120200579 | Process Device Context Switching - Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device. | 08-09-2012 |
20130135327 | Saving and Restoring Non-Shader State Using a Command Processor - Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core. | 05-30-2013 |
20130141446 | Method and Apparatus for Servicing Page Fault Exceptions - A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling request to a translation mechanism is sent when the page fault is detected. A fault handling response corresponding to the detected page fault from the translation mechanism is received. Confirmation that the detected page fault has been handled through performing page mapping based on the fault handling response is received. | 06-06-2013 |
20130141447 | Method and Apparatus for Accommodating Multiple, Concurrent Work Inputs - A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list. | 06-06-2013 |
20130145202 | Handling Virtual-to-Physical Address Translation Failures - A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed. | 06-06-2013 |
20130155077 | Policies for Shader Resource Allocation in a Shader Core - A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing. | 06-20-2013 |
20130155079 | Saving and Restoring Shader Context State - Provided is a method for processing a command in a computing system including an accelerated processing device (APD) having a command processor. The method includes executing an interrupt routine to save one or more contexts related to a first set of instructions on a shader core in response to an instruction to preempt processing of the first set of instructions. | 06-20-2013 |
20130160017 | Software Mechanisms for Managing Task Scheduling on an Accelerated Processing Device (APD) - Embodiments describe herein provide a method of for managing task scheduling on a accelerated processing device. The method includes executing a first task within the accelerated processing device (APD), monitoring for an interruption of the execution of the first task, and switching to a second task when an interruption is detected. | 06-20-2013 |
20130160019 | Method for Resuming an APD Wavefront in Which a Subset of Elements Have Faulted - A method resumes an accelerated processing device (APD) wavefront in which a subset of elements have faulted. A restore command for a job including a wavefront is received. A list of context states for the wavefront is read from a memory associated with a APD. An empty shell wavefront is created for restoring the list of context states. A portion of not acknowledged data is masked over a portion of acknowledged data within the restored wavefronts. | 06-20-2013 |
20130297950 | VOLTAGE ADJUSTMENT BASED ON LOAD LINE AND POWER ESTIMATES - A method and system for determining voltage supplied to a processor from a voltage regulator when the voltage cannot be directly measured. | 11-07-2013 |
20130318372 | DYNAMIC LOAD STEP CALCULATION FOR LOAD LINE ADJUSTMENT - A method of controlling voltage in a circuit is provided. Within the circuit, a block of an electrical component provides an indication that it desires to switch states (such as from off to on, on to off, or from one speed to another). The change in states requires a different current draw by the electrical component block. The indication is received by an electrical component that controls the voltage of the circuit. The electrical component that controls the voltage then issues a signal granting permission for the electrical component block to switch states. This permission signal is received by the electrical component and the electrical component block changes state. | 11-28-2013 |
20140022263 | METHOD FOR URGENCY-BASED PREEMPTION OF A PROCESS - The desire to use an Accelerated Processing Device (APD) for general computation has increased due to the APD's exemplary performance characteristics. However, current systems incur high overhead when dispatching work to the APD because a process cannot be efficiently identified or preempted. The occupying of the APD by a rogue process for arbitrary amounts of time can prevent the effective utilization of the available system capacity and can reduce the processing progress of the system. Embodiments described herein can overcome this deficiency by enabling the system software to pre-empt a process executing on the APD for any reason. The APD provides an interface for initiating such a pre-emption. This interface exposes an urgency of the request which determines whether the process being preempted is allowed a grace period to complete its issued work before being forced off the hardware. | 01-23-2014 |
20140181536 | USING TEMPERATURE MARGIN TO BALANCE PERFORMANCE WITH POWER ALLOCATION - A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile. | 06-26-2014 |
20140340527 | METHODS AND APPARATUS FOR STORING AND DELIVERING COMPRESSED DATA - A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link along with corresponding audio and/or video data in real time. | 11-20-2014 |
20140344486 | METHODS AND APPARATUS FOR STORING AND DELIVERING COMPRESSED DATA - Methods and apparatus for storing and delivering compressed data are disclosed. In one embodiment, a direct memory access (DMA) unit with a lossless coder/decoder (CODEC) receives uncompressed data. The direct memory access unit then compresses the uncompressed data to produce lossless compressed data, and stores the lossless compressed data in a memory, wherein the compressing operation and the storing operation are each part of a direct memory access (DMA) write operation. In another embodiment, the direct memory access (DMA) unit receives lossless compressed data. The direct memory access unit then decompresses the compressed data to produce lossless decompressed data, and delivers the decompressed data to an output device, wherein the decompressing operation and the receiving operation are each part of a direct memory access (DMA) read operation. | 11-20-2014 |
20140344592 | METHODS AND APPARATUS FOR POWERING UP AN INTEGRATED CIRCUIT - A power supply ( | 11-20-2014 |
20140344947 | METHOD AND APPARATUS FOR HANDLING STORAGE OF CONTEXT INFORMATION - A method and apparatus is provided for improving security of context information of processing circuitry of a processing device. In one example, the method and apparatus stores context information of the processing circuitry on an external storage medium at a first location as part of the processing circuitry entering a first power state, and stores the context information of the processing circuitry on the storage medium at a second location as part of the processing circuitry entering a second, later and different power state. | 11-20-2014 |
20150052622 | METHOD AND APPARATUS FOR MONITORING PERFORMANCE FOR SECURE CHIP OPERATION - A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode. | 02-19-2015 |