Patent application number | Description | Published |
20100193901 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer. | 08-05-2010 |
20110024833 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region. | 02-03-2011 |
20110027988 | METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer. | 02-03-2011 |
20110237047 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process. | 09-29-2011 |
20130228859 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first region and a second region, a buried gate arranged in the first region, and an oxidation prevention barrier surrounding the first region. | 09-05-2013 |
20140187030 | SEMICONDUCTOR DEVICE WITH DUAL WORK FUNCTION GATE STACKS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer. | 07-03-2014 |
20140256125 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer. | 09-11-2014 |
20150123167 | METHOD AND GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS - A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region. | 05-07-2015 |