Patent application number | Description | Published |
20120070981 | ATOMIC LAYER DEPOSITION OF A COPPER-CONTAINING SEED LAYER - The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent. | 03-22-2012 |
20130270513 | ELECTROPOSITIVE METAL CONTAINING LAYERS FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (Å)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals. | 10-17-2013 |
20130273261 | METHOD OF INCREASING AN ENERGY DENSITY AND AN ACHIEVABLE POWER OUTPUT OF AN ENERGY STORAGE DEVICE - Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure. | 10-17-2013 |
20140034906 | CARBON NANOTUBE SEMICONDUCTOR DEVICES AND DETERMINISTIC NANOFABRICATION METHODS - Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications. | 02-06-2014 |
20140084387 | NON-PLANAR III-V FIELD EFFECT TRANSISTORS WITH CONFORMAL METAL GATE ELECTRODE & NITROGEN DOPING OF GATE DIELECTRIC INTERFACE - A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface. | 03-27-2014 |
20140117559 | PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) - Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW | 05-01-2014 |
20140185260 | NANOSTRUCTURED ELECTROLYTIC ENERGY STORAGE DEVICES - In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer. A separator separates the first and second nanostructured substrates and allows ions of an electrolyte to pass through the separator. The structure may be a nanostructured electrolytic capacitor with the first nanostructured substrate forming a positive electrode and the second nanostructured substrate forming a negative electrode of the capacitor. | 07-03-2014 |
20140335918 | ENERGY STORAGE DEVICE, METHOD OF MANUFACTURING SAME, AND MOBILE ELECTRONIC DEVICE CONTAINING SAME - An energy storage device comprises a first porous semiconducting structure ( | 11-13-2014 |
20150072498 | NON-PLANAR III-V FIELD EFFECT TRANSISTORS WITH CONFORMAL METAL GATE ELECTRODE & NITROGEN DOPING OF GATE DIELECTRIC INTERFACE - A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface. | 03-12-2015 |