Patent application number | Description | Published |
20100195408 | Non-Body Contacted Sense Amplifier with Negligible History Effect - In a method of mitigating hysteresis effect in a sense amplifier circuit, a data value is sensed from a data source with the sense amplifier during a first period. The data value is stored in a latch. The data valued stored in the latch is inverted, thereby generating an inverted data value. The data source is isolated from the sense amplifier and the inverted data value is read with the sense amplifier during a second period immediately following the first period. | 08-05-2010 |
20120033508 | LEVEL SHIFTER FOR USE WITH MEMORY ARRAYS - In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided. | 02-09-2012 |
20130201753 | IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM - A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line. | 08-08-2013 |
20130286717 | IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS - A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array. | 10-31-2013 |
20140112060 | SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE - An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage. | 04-24-2014 |
20140112064 | SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE - An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage. | 04-24-2014 |
Patent application number | Description | Published |
20090285039 | METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WRITE ASSIST ON COLUMN SELECTED SRAM CELLS - A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read. | 11-19-2009 |
20090287971 | METHOD AND APPARATUS FOR TESTING A RANDOM ACCESS MEMORY DEVICE - A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic. | 11-19-2009 |
20090323445 | High Performance Read Bypass Test for SRAM Circuits - A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode. | 12-31-2009 |
20110292748 | IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE PUMPED ARRAYS - A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value. | 12-01-2011 |
20120081949 | Active Bit Line Droop for Read Assist - A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved. | 04-05-2012 |
Patent application number | Description | Published |
20090277121 | MASONRY BLOCK AND METHOD OF MAKING SAME - Molds and processes that permit high-speed, mass production of retaining wall blocks having patterned or other processed front faces, as well as retaining wall blocks formed by such processes. The invention permits the front face of the block to be impressed with a pattern or otherwise directly processed, to allow the formation of pre-determined block front faces, while at the same time facilitating high-speed, high-volume production of blocks. Pre-determined front faces can include front faces having pre-determined patterns and textures, front faces having pre-determined shapes, front faces made from different material(s) than the remainder of the block, and combinations thereof. | 11-12-2009 |
20100155999 | CONCRETE BLOCK AND METHOD OF MAKING SAME - Molds and processes that permit high-speed, mass production of retaining wall blocks having patterned or other processed front faces, as well as retaining wall blocks formed by such processes. The invention permits the front face of the block to be impressed with a pattern or otherwise directly processed, to allow the formation of pre-determined block front faces, while at the same time facilitating high-speed, high-volume production of blocks. A mirror image of the desired pattern can be created on a stripper shoe by selecting a desired three-dimensional surface from a naturally occurring or man made object and digitally scanning the selected three-dimensional pattern to create scanned data. The scanned data can then be used to machine a face of the stripper shoe that is the mirror image of the selected pattern. | 06-24-2010 |
20110083656 | BLOCK SPLITTING ASSEMBLY AND METHOD - The invention relates to equipment and related methods for producing concrete blocks. The equipment and methods described herein utilize splitting assemblies having larger projections and/or smaller projections or peaks disposed on at least one side of a splitting line and which engage the workpiece as it is split into at least two pieces. | 04-14-2011 |
20120175808 | CONCRETE BLOCK AND METHOD OF MAKING SAME - Molds and processes that permit high-speed, mass production of retaining wall blocks having patterned or other processed front faces, as well as retaining wall blocks formed by such processes. The invention permits the front face of the block to be impressed with a pattern or otherwise directly processed, to allow the formation of pre-determined block front faces, while at the same time facilitating high-speed, high-volume production of blocks. A mirror image of the desired pattern can be created on a stripper shoe by selecting a desired three-dimensional surface from a naturally occurring or man made object and digitally scanning the selected three-dimensional pattern to create scanned data. The scanned data can then be used to machine a face of the stripper shoe that is the mirror image of the selected pattern. | 07-12-2012 |
20120312291 | BLOCK SPLITTING ASSEMBLY AND METHOD - The invention relates to equipment and related methods for producing concrete blocks. The equipment and methods described herein utilize splitting assemblies having larger projections and/or smaller projections or peaks disposed on at least one side of a splitting line and which engage the workpiece as it is split into at least two pieces. | 12-13-2012 |
20130334731 | CONCRETE BLOCK AND METHOD OF MAKING SAME - Molds and processes that permit high-speed, mass production of retaining wall blocks having patterned or other processed front faces, as well as retaining wall blocks formed by such processes. The invention permits the front face of the block to be impressed with a pattern or otherwise directly processed, to allow the formation of pre-determined block front faces, while at the same time facilitating high-speed, high-volume production of blocks. A mirror image of the desired pattern can be created on a stripper shoe by selecting a desired three-dimensional surface from a naturally occurring or man made object and digitally scanning the selected three-dimensional pattern to create scanned data. The scanned data can then be used to machine a face of the stripper shoe that is the mirror image of the selected pattern. | 12-19-2013 |
20130340739 | BLOCK SPLITTING ASSEMBLY AND METHOD - The invention relates to equipment and related methods for producing concrete blocks. The equipment and methods described herein utilize splitting assemblies having larger projections and/or smaller projections or peaks disposed on at least one side of a splitting line and which engage the workpiece as it is split into at least two pieces. | 12-26-2013 |
Patent application number | Description | Published |
20100161138 | DISTRIBUTED MONITORING AND CONTROL FLUID HANDLING SYSTEM - A fluid handling control/monitoring system is divided into a network of modular, intelligent components. These individual components are generally specific to a certain function within the system and contain all the intelligence necessary to perform that function without external guidance. Examples of the different types of components include but are not limited to: human-machine interface (HMI), fluid control, heater control, motor control, field-bus communications and the like. While each type of board is specialized in function, it may control several items of the same nature. For instance, a heater control may be able to control several heaters on one system. Similarly, a fluid board may have the ability to receive input from more than one flow meter and then control fluid flow of more than one point. An example might be a plural component metering and dispensing system where two fluid components have to be combined in a precise mix ratio. | 06-24-2010 |
20110103025 | MODULAR ELECTRONIC SYSTEM - Off-the-shelf electronic packages eliminate the much of the need for hardware redesign for each product. The base unit has a base plastic housing and a power/communication board. The component module is comprised of a mid-section plastic housing, a common board, a component board, panels with connectors and a housing cover. The component board is unique board to each platform and could be, for example, a fluid control module, a low power temperature control module, a gateway module, a USB module, etc. | 05-05-2011 |
20120121439 | HYDRAULIC POWER MODULE - The hydraulic power module | 05-17-2012 |